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US5166644A
Expired / Lapsed
US
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Pll synthesizer circuit
Assignee: Fujitsu VLSI Ltd
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Filing: 1991-12-26
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Granted: 1992-11-24
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Expires: 2011-12-26
Abstract
Abstract A PLL synthesizer circuit includes a lowpass filter including capacitors for restricting an output voltage of the lowpass filter, a charge pump circuit for controlling the output voltage of the lowpass filter by charging or discharging the capacitors of the lowpass filter, a voltage controlled oscillator for outputting an output signal having a frequency which is controlled by the output voltage of the lowpass filter, a frequency divider for frequency-dividing the output signal of the voltage controlled oscillator to output a comparison signal and having a variable frequency dividing ratio, a phase comparator for comparing a phase of a reference signal having a predetermined frequency and a phase of the comparison signal output from the frequency divider to output phase error information which indicates a phase lead and a phase lag of the comparison signal with respect to the reference signal, and a charge pump control circuit for forming control information based on the phase error information when switching a frequency of the output signal of the voltage controlled oscillator from a first frequency to a second frequency and for supplying the control information to the charge pump circuit. The charge pump circuit charges or discharges the capacitors of the lowpass filter independently of the reference signal based on the control information until the output signal of the voltage controlled oscillator reaches the second frequency, so as to raise or lower the output voltage of the lowpass filter depending on the charging or discharging. The output signal of the voltage controlled oscillator is used as an output signal of the PLL synthesizer circuit.
Inventors
- 👤 Shinji Saito
- 👤 Akira Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:20
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/10; H03L7/16; H03L7/18; H03L7/183
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
303 words
A phase locked loop synthesizer circuit comprising: a lowpass filter including capacitors for restricting an output voltage of the lowpass filter; a charge pump circuit, coupled to the lowpass filter, for controlling the output voltage of the lowpass filter by charging or discharging the capacitors of the lowpass filter; a voltage controlled oscillator, coupled to the lowpass filter, for outputting an output signal having a frequency which is controlled by the output voltage of the lowpass filter; a frequency divider, coupled to the voltage controlled oscillator, for frequency-dividing the output signal of the voltage controlled oscillator and for outputting a comparison signal, said frequency divider having a variable frequency dividing ratio; a phase comparator, coupled to the frequency divider, for comparing the phase of a reference signal having a predetermined frequency and the phase of the comparison signal output from the frequency divider, said phase comparator outputting phase error information which indicates a phase lead and a phase lag of the comparison signal with respect to the reference signal; and a charge pump control circuit, coupled between the phase comparator and the charge pump circuit, for forming control information based on the phase error information when switching the frequency of the output signal of the voltage controlled oscillator from a first frequency to a second frequency, and for supplying the control information to the charge pump circuit, said charge pump circuit charging or discharging the capacitors of the lowpass filter independently of the reference signal based on the control information until the output signal of the voltage controlled oscillator reaches the second frequency, so as to raise or lower the output voltage of the lowpass filter depending on the charging or discharging, the output signal of the voltage controlled oscillator being used as an output signal of the phase locked loop synthesizer circuit.
Claim 2
Dependent Claim
303 words
A phase locked loop synthesizer circuit comprising: a lowpass filter including capacitors for restricting an output voltage of the lowpass filter; a charge pump circuit, coupled to the lowpass filter, for controlling the output voltage of the lowpass filter by charging or discharging the capacitors of the lowpass filter; a voltage controlled oscillator, coupled to the lowpass filter, for outputting an output signal having a frequency which is controlled by the output voltage of the lowpass filter; a frequency divider, coupled to the voltage controlled oscillator, for frequency-dividing the output signal of the voltage controlled oscillator and for outputting a comparison signal, said frequency divider having a variable frequency dividing ratio; a phase comparator, coupled to the frequency divider, for comparing the phase of a reference signal having a predetermined frequency and the phase of the comparison signal output from the frequency divider, said phase comparator outputting phase error information which indicates a phase lead and a phase lag of the comparison signal with respect to the reference signal; and a charge pump control circuit, coupled between the phase comparator and the charge pump circuit, for forming control information based on the phase error information when switching the frequency of the output signal of the voltage controlled oscillator from a first frequency to a second frequency, and for supplying the control information to the charge pump circuit, said charge pump circuit charging or discharging the capacitors of the lowpass filter independently of the reference signal based on the control information until the output signal of the voltage controlled oscillator reaches the second frequency, so as to raise or lower the output voltage of the lowpass filter depending on the charging or discharging, the output signal of the voltage controlled oscillator being used as an output signal of the phase locked loop synthesizer circuit.
Claim 3
Dependent Claim
34 words
The phase locked loop synthesizer circuit as claimed in claim 1, wherein said charge pump control circuit forms the control information based on the phase error information in response to an external clock signal.
Claim 4
Dependent Claim
64 words
The phase locked loop synthesizer circui as claimed in claim 1, which further comprises a crystal oscillator for outputting a predetermined signal and a reference frequency divider for frequency-dividing the predetermined signal to output the reference signal together with a clock signal, and said charge pump control circuit forms the control information based on the phase error information in response to the clock signal.
Claim 5
Dependent Claim
33 words
The phase locked loop synthesizer circuit as claimed in claim 1, wherein said charge pump circuit charges or discharges the capacitors of the lowpass filter substantially without interruption based on the control information.
Claim 6
Dependent Claim
62 words
The phase locked loop synthesizer circuit as claimed in claim 1, wherein said phase comparator outputs the phase error information which is made up of a first signal which indicates the phase lead of the comparison signal with respect to the reference signal and a second signal which indicates the phase lag of the comparison signal with respect to the reference signal.
Claim 7
Dependent Claim
45 words
The phase locked loop synthesizer circuit as claimed in claim 5, wherein said charge pump control circuit outputs the control information which is made up of a third signal which corresponds to the first signal and a fourth signal which corresponds to the second signal.
Claim 8
Dependent Claim
51 words
The phase locked loop synthesizer circuit as claimed in claim 5, wherein said charge pump circuit includes first and second transistors of mutually opposite transistor types coupled in series between a power source and ground, and said first and second transistors are respectively controlled based on the first and second signals.
Claim 9
Dependent Claim
23 words
The phase locked loop synthesizer circuit as claimed in claim 7, wherein said first and second transistors respectively ar PNP and NPN transistors.
Claim 10
Dependent Claim
23 words
The phase locked loop synthesizer circuit as claimed in claim 7, wherein said first and second transistors respectively are P-channel and N-channel MOSFETS.
Claim 11
Dependent Claim
46 words
The phase locked loop synthesizer circuit as claimed in claim 7, wherein said first and second transistors of the charge pump circuit are coupled to each other at a node, and said lowpass filter receives the output signal of the charge pump circuit via the node.
References Cited (Backward Citations)
US4987387A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |