Special effect generator with limited read address calculation region

Claim 2

A special effect generator for video signals comprising: memory means for storing video signals representing an image; a source of data indicating by x and y addresses a calculating region having coordinate boundaries for a special effect pattern that is smaller than the image; read address generating means coupled to said memory means and said source of data for generating a read address for addressing said video signals stored in said memory means associated with the special effect pattern; and address generation control means coupled to said source of data and to said read address generating means for limiting the generation of said read address in x and y directions based on said coordinate boundaries in response to the data indicating the calculating region from said source, so that only those read addresses actually required for the special effect are calculated.

Claim 3

The special effect generator according to claim 1, wherein said address generation control means receives the data indicating the calculating region for the special effect pattern from said source of data and includes x address limiting means for producing an x address limiting signal fed to said read address generating means for limiting addresses in the x direction to the calculating region and y address limiting means for producing a y address limiting signal fed to said read address generating means for limiting addresses in the y direction to the calculating region.

Claim 4

The special effect generator according to claim 2, wherein said x address limiting means includes a first register for setting an x start address, a second register for setting an x end address, a first comparator being supplied with said x start address stored in said first register, a second comparator being supplied with said x end address set in said second register, a first counter receiving synch signals of said video signals and for supplying an x display address to said first and second comparators, said first comparator comparing said x start address to said x display address and generating a signal when said x display address is larger than said x start address and said second comparator comparing said x end address to said x display address and generating a signal when said x display address is smaller than said end address, while said y address limiting means includes a third register for setting a y start address, a fourth register for setting a y end address, a third comparator being supplied with said y start address set in said third register, a fourth comparator being supplied with said y end address set in said fourth register, and a second counter receiving synch signals of said video signals and for supplying a y display address to said third and fourth comparators, said third comparator comparing said y start address to said y display address and generating a signal when said y display address is larger than said y start address and said second comparator comparing said y end address to said y display address and generating a signal when said y display address is smaller than said end address.

Claim 5

The special effect generator according to claim 3, wherein said x address limiting means further includes a first AND gate coupled to said first and second comparators for generating said x address limiting signal to be supplied to said read address generating means, and said y address limiting means further includes a second AND gate coupled to said third and fourth comparators for generating said y address limiting signal to be supplied to said read address generating means.

Claim 6

The special effect generator according to claim 4, wherein said x display address from said first counter and said y display address from said second counter are also supplied to said read address generating means.