US5165038A
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Global registers for a multiprocessor system
Assignee: Morgan Stanley and Co LLC
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Filing: 1990-06-11
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Granted: 1992-11-17
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Expires: 2010-06-11
Abstract
Abstract Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.
Inventors
- 👤 Douglas R. Beard
- 👤 George A. Spix
- 👤 Edward C. Miller
- 👤 II Robert E. Strout
- 👤 Anthony R. Schooler
- 👤 Alexander A. Silbey
- 👤 Brian D. Vanderwarn
- 👤 Jimmie R. Wilson
- 👤 Richard E. Hessel
- 👤 Andrew E. Phelps
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:06
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375; G06F15/17; G06F15/17381; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8092; G06F8/00; G06F8/40; G06F8/41; G06F8/43; G06F8/433; G06F8/45; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30021; G06F9/3004; G06F9/30076; G06F9/30087; G06F9/30094; G06F9/30098; G06F9/30101; G06F9/3012; G06F9/30145; G06F9/30149; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3838
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
272 words
A system of global registers for a multiprocessor system comprising: a plurality of global register files, each global register file containing a plurality of global register means for storing data; two or more requestors in the multiprocessor system, each requestor having a processor with an instruction decode means for decoding a plurality of instructions, at least one of which comprises a request to the system of global registers, each request comprising information supplied by the requestor, including: an address specifying a selected global register file and a selected global register means, a data value, and an operation command specifying an operation to be performed on the selected global register means using the data value; a plurality of access path means operably connected between the requestors and the global register files for transferring one or more requests to and from the global register files from one or ore requestors in the multiprocessor system, a plurality of switch means operably connected to the global register files and the access path means for routing the requests to the selected global register file and the selected global register means within the global register file in response to the address contained in the request and for routing data from the selected global register file and the selected global register means to be returned to the requestor; and for each global register file, an arithmetic and logical unit means operably connected to that global register file for performing arithmetic and logical operations on the selected global register means associated with that global register file and the data value in response to the operation command contained in the request.
Claim 2
Independent Claim
272 words
A system of global registers for a multiprocessor system comprising: a plurality of global register files, each global register file containing a plurality of global register means for storing data; two or more requestors in the multiprocessor system, each requestor having a processor with an instruction decode means for decoding a plurality of instructions, at least one of which comprises a request to the system of global registers, each request comprising information supplied by the requestor, including: an address specifying a selected global register file and a selected global register means, a data value, and an operation command specifying an operation to be performed on the selected global register means using the data value; a plurality of access path means operably connected between the requestors and the global register files for transferring one or more requests to and from the global register files from one or ore requestors in the multiprocessor system, a plurality of switch means operably connected to the global register files and the access path means for routing the requests to the selected global register file and the selected global register means within the global register file in response to the address contained in the request and for routing data from the selected global register file and the selected global register means to be returned to the requestor; and for each global register file, an arithmetic and logical unit means operably connected to that global register file for performing arithmetic and logical operations on the selected global register means associated with that global register file and the data value in response to the operation command contained in the request.
Claim 3
Dependent Claim
33 words
The system of global registers of claim 1 wherein one of the arithmetic and logical operations to be performed by the arithmetic and logical unit means is a fetch and conditional add instruction.
Claim 4
Dependent Claim
30 words
The system of global registers of claim 1 wherein the access path means further comprises arbitration means for determining the priority among multiple requests for the same global register file.
Claim 5
Dependent Claim
42 words
The system of global registers of claim 1 wherein at least one of the arithmetic and logical operations to be performed by the arithmetic and logic unit means is an atomic resource allocation operation in the form of an uninterrupted read-modify-write operation.
Claim 6
Dependent Claim
82 words
The system of global registers of claim 1 wherein the multiprocessor system is a highly parallel multiprocessor systems organized as a plurality of clusters, each cluster including a plurality of requestors comprised of a plurality of processors and a plurality of input/output controllers which are operably connected to a unique subset of the set of global registers and wherein each subset of global registers ma be accessed both by the requestors within and without the cluster associated that subset of global registers.
Claim 7
Dependent Claim
29 words
The system of global registers of claim 1 wherein the requestors are comprised of a plurality of processors and a plurality of input/output controllers that comprise the multiprocessor system.
Claim 8
Dependent Claim
32 words
The system of global registers of claim 6 wherein the address generated by the processors is comprised of a base address, a mask address, an offset address and an instruction field value.
Claim 9
Dependent Claim
44 words
The system of global registers of claim 7 wherein an operating system for the multiprocessor system assigns the processors to a process by assigning a unique set of global registers to a process by specifying the offset address and mask address for the process.
Claim 10
Dependent Claim
35 words
The system of global registers of claim 1 wherein the access path means is comprised of an address pipe means for transferring the address and command and a data pipe means for transferring the data.
Claim 11
Dependent Claim
27 words
The system of global registers of claim 1 wherein the global registers are capable of pipelining multiple parallel requests on consecutive clock cycles of the multiprocessor system.
Claim 12
Independent Claim
351 words
A system of global registers for a multiprocessor system having two or more processors for making requests to a selected set of global registers, each request comprising information supplied by the requestor, including an address specifying the selected set of global registers, a data value, and an operation command specifying an operation to be performed on the selected set of global registers using the data value, the address being comprised of a base address, a mask address, and an offset address such that an operating system program for the multiprocessor system assigns a set of global registers to a process by specifying the offset address and mask address for the process, the system of global registers comprising: a plurality of global register files, each global register file containing a plurality of global register means for storing data; a plurality of access path means operably connected between the requestors and the global register files for transferring one or more requests to and from the global register files from the processors in the multiprocessor system, the access path means including: arbitration means for determining the priority among multiple requests for the same global register file; address pipe means for transferring the address and command; and data pipe means for transferring the data; a plurality of switch means operably connected the global register files and the access path means for routing the requests to the selected global register file and the selected global register means within the global register file in response to the address contained in the request and for routing data from the selected global register file and the selected global register means to be returned to the processor; and arithmetic and logical unit means operably connected to each global register file for performing arithmetic and logical operations in the form of atomic operations on the selected global register means associated with that global register file and the data value in response to the operation command contained in the request, such that the sets of global registers are capable of pipelining multiple parallel requests on consecutive clock cycles of the multiprocessor system.
Claim 13
Independent Claim
351 words
A system of global registers for a multiprocessor system having two or more processors for making requests to a selected set of global registers, each request comprising information supplied by the requestor, including an address specifying the selected set of global registers, a data value, and an operation command specifying an operation to be performed on the selected set of global registers using the data value, the address being comprised of a base address, a mask address, and an offset address such that an operating system program for the multiprocessor system assigns a set of global registers to a process by specifying the offset address and mask address for the process, the system of global registers comprising: a plurality of global register files, each global register file containing a plurality of global register means for storing data; a plurality of access path means operably connected between the requestors and the global register files for transferring one or more requests to and from the global register files from the processors in the multiprocessor system, the access path means including: arbitration means for determining the priority among multiple requests for the same global register file; address pipe means for transferring the address and command; and data pipe means for transferring the data; a plurality of switch means operably connected the global register files and the access path means for routing the requests to the selected global register file and the selected global register means within the global register file in response to the address contained in the request and for routing data from the selected global register file and the selected global register means to be returned to the processor; and arithmetic and logical unit means operably connected to each global register file for performing arithmetic and logical operations in the form of atomic operations on the selected global register means associated with that global register file and the data value in response to the operation command contained in the request, such that the sets of global registers are capable of pipelining multiple parallel requests on consecutive clock cycles of the multiprocessor system.
Claim 14
Dependent Claim
70 words
The system of global registers of claim 11 wherein the multiprocessor system is a highly parallel multiprocessor systems organized as a plurality of clusters, each cluster including a plurality of processors which are operably connected to a unique subset of the set of global registers and wherein each subset of global registers may be accessed both by the processors within and without the cluster associated that subset of global registers.
References Cited (Backward Citations)
US3308436A
Cited
US3970993A
Cited
US4015243A
Cited
US4240143A
Cited
US4523273A
Cited
US4814980A
Cited
US4924380A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |