US5164814A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with customized wiring
Assignee: Toshiba Corp
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Filing: 1991-09-04
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Granted: 1992-11-17
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Expires: 2011-09-04
Abstract
Abstract A semiconductor device has a semiconductor substrate, MOS transistors formed in the semiconductor substrate, a wiring pattern formed on the semiconductor substrate, for wiring the MOS transistors, and a passivation layer covering the wiring pattern. In the semiconductor device, the wiring pattern includes a plurality of connecting sections each selectively set to a conductive state by conductive material filled in an opening formed in the insulating layer.
Inventors
- 👤 Katsuya Okumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:06
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/34; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
87 words
A programmable semiconductor device, capable of being programmed without fabricating a wiring layer, comprising: a semiconductor body; semiconductor elements in said semiconductor body; a wiring pattern on said semiconductor body for wiring said semiconductor elements, the wiring pattern including discontinuous portions, each discontinuous portion having a first section and a second section, and other portions; and an insulating layer covering said wiring pattern and defining a plurality of openings, each of the openings exposing a discontinuous portion having the first section electrically isolated from the second section.
Claim 2
Dependent Claim
87 words
A programmable semiconductor device, capable of being programmed without fabricating a wiring layer, comprising: a semiconductor body; semiconductor elements in said semiconductor body; a wiring pattern on said semiconductor body for wiring said semiconductor elements, the wiring pattern including discontinuous portions, each discontinuous portion having a first section and a second section, and other portions; and an insulating layer covering said wiring pattern and defining a plurality of openings, each of the openings exposing a discontinuous portion having the first section electrically isolated from the second section.
Claim 3
Dependent Claim
22 words
A semiconductor device according to claim 1, wherein said discontinuous portions include first and second conductive layers arranged adjacent to each other.
Claim 4
Dependent Claim
31 words
A semiconductor device according to claim 2, wherein said opening each have a portion of said first conductive layer and a portion of said second conductive layer projecting into said openings.
Claim 5
Dependent Claim
26 words
A semiconductor device according to claim 3, wherein a distance between said first and second conductive layers is less than a thickness of said insulating layer.
Claim 6
Dependent Claim
30 words
A semiconductor device according to claim 4, wherein the distance between said first and second conductive layers is not more than a thicknesses of said first and second conductive layers.
Claim 7
Dependent Claim
26 words
A semiconductor device according to claim 2, wherein a distance between said first and second conductive layers is less than a thickness of said insulating layer.
Claim 8
Dependent Claim
30 words
A semiconductor device according to claim 2, wherein a distance between said first and second conductive layers is not more than a thicknesses of said first and second conductive layers.
Claim 9
Dependent Claim
50 words
A semiconductor device according to claim 1, wherein said semiconductor elements include MOS transistors each serving as a memory cell, said wiring pattern includes wiring lines for terminals of said MOS transistors, and said discontinuous portions are formed in the wiring lines for a predetermined terminal of said MOS transistor.
Claim 10
Dependent Claim
44 words
A semiconductor device according to claim 8, wherein said MOS transistor has a source and drain formed in a surface of said semiconductor body, and a gate formed over and insulated from a region of said semiconductor body located between said source and drain.
Claim 11
Dependent Claim
93 words
A semiconductor device according to claim 9, wherein said wiring lines include a first wiring line connected to supply a reading voltage to the gate of said MOS transistor, a second wiring line connected between a reference potential terminal and the source of said MOS transistor, and a third wiring line; said third wiring line including a metal layer connected to the drain of said MOS transistor and a metal layer connected to a power source terminal via a load circuit; and said discontinuous portion is formed of ends of said metal layers.
Claim 12
Dependent Claim
97 words
A programmable semiconductor device, capable of being programmed without fabricating a wiring layer, comprising: a semiconductor body; semiconductor elements in the semiconductor body; a wiring pattern on the semiconductor body for wiring said semiconductor elements, the wiring pattern including discontinuous portions, each discontinuous portion defining a space between a first section of a first material and a second section of the first material, the space being filled with a material different from the first material, and other portions; and an insulator covering the wiring pattern to fill the space defined by each one of the discontinuous portions.
Claim 13
Dependent Claim
97 words
A programmable semiconductor device, capable of being programmed without fabricating a wiring layer, comprising: a semiconductor body; semiconductor elements in the semiconductor body; a wiring pattern on the semiconductor body for wiring said semiconductor elements, the wiring pattern including discontinuous portions, each discontinuous portion defining a space between a first section of a first material and a second section of the first material, the space being filled with a material different from the first material, and other portions; and an insulator covering the wiring pattern to fill the space defined by each one of the discontinuous portions.
Claim 14
Dependent Claim
24 words
A semiconductor device according to claim 11, wherein a distance between the first and second sections is less than a thickness of the insulator.
Claim 15
Dependent Claim
25 words
A semiconductor device according to claim 11, wherein a distance between the first and second sections is no greater than a thickness of the insulator.
Claim 16
Dependent Claim
60 words
A programmable semiconductor device according to claim 11, further including a power source, and wherein the semiconductor elements include MOS transistors coupled to the wiring pattern in a memory configuration, each MOS transistor having a current path, and wherein one of the discontinuous portions is coupled between the current path of one of the MOS transistors and the power source.
Claim 17
Dependent Claim
91 words
A programmable semiconductor device, capable of being programmed without fabricating a wiring layer, resulting from performing a process comprising the steps of: forming semiconductor elements on a semiconductor body; forming first portions of a wiring pattern on the semiconductor body, for wiring the semiconductor elements; forming N discontinuous portions of the wiring pattern on a layer of the semiconductor body; and covering the wiring pattern with an insulator to fill each one of the N discontinuous portions with the insulator, after the step of forming first portions of the wiring pattern.
Claim 18
Dependent Claim
91 words
A programmable semiconductor device, capable of being programmed without fabricating a wiring layer, resulting from performing a process comprising the steps of: forming semiconductor elements on a semiconductor body; forming first portions of a wiring pattern on the semiconductor body, for wiring the semiconductor elements; forming N discontinuous portions of the wiring pattern on a layer of the semiconductor body; and covering the wiring pattern with an insulator to fill each one of the N discontinuous portions with the insulator, after the step of forming first portions of the wiring pattern.
References Cited (Backward Citations)
US4673966A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |