A p channel mis type semiconductor device

Claim 2

A P channel MIS type semiconductor device, comprising: a substrate having an N conductivity type semiconductor surface region; a gate insulator layer formed on said N conductivity type region; a channel region formed under the gate insulator layer; a gate electrode formed on said gate insulator layer; source and drain regions of P conductivity type with each having a same P-type impurity element and formed in the semiconductor surface region on opposite sides of the channel region, each of said source and drain regions including first and second regions respectively, with said first region being of a higher impurity concentration than said second region in an area under each of a source and drain electrode formed on said source and drain regions, respectively; a channel side edge of the first region arranged on or outside of a channel side edge of the second region and contacting the channel region; and the second region being of a higher impurity concentration than the first region in an area along a surface of the source and drain regions under an edge of the gate insulator layer.

Claim 3

The MIS type semiconductor device according to claim 1, further comprising; source and drain electrodes formed on a surface of said source and drain regions.

Claim 4

The MIS type semiconductor device according to claim 1, wherein the channel side edge of said first region is separated from the channel side edge of said second region.

Claim 5

The MIS type semiconductor device according to claim 1, wherein the channel side edge of said first region is arranged on the channel side edge of said second region.

Claim 6

The MIS type semiconductor device according to claim 1, wherein a P type channel ion-implanted layer is formed at a surface of said N type conductivity region.

Claim 7

The MIS type semiconductor device according to claim 1, wherein said first region is deeper than said second region.

Claim 8

The MIS type semiconductor device according to claim 1, further comprising: side wall insulators being self-aligned to said gate electrode; wherein said first region is self-aligned to said gate electrode and said side wall insulators, and said second regions are self-aligned to said gate electrode.

Claim 9

The semiconductor device according to claim 1, wherein the impurity concentration of said first and second region is boron.

Claim 10

The MIS type semiconductor device according to claim 1, wherein a length of said gate electrode along a direction of said source and drain regions is less than 1 μm.

Claim 11

The MIS type semiconductor device according to claim 1, wherein a P type impurity concentration curve along a surface of said second region has a portion being above a tail of said first region.

Claim 12

A P channel MIS type semiconductor device, comprising: a substrate having a semiconductor surface portion; an N conductivity type region formed in the semiconductor surface portion; a first gate insulator layer formed on the N conductivity type region; a first channel region formed under the first gate insulator layer; a first gate electrode formed on said first gate insulator layer; first source and first drain regions of P conductivity type with each having a same P-type impurity element and formed in the semiconductor surface region on opposite sides of the first channel region, each of said first source and first drain regions including first and second regions respectively, with said first region being of a higher impurity concentration than said second region in an area under each of a source and drain electrode formed on said first source and said first drain regions, respectively; a channel side edge of the first region arranged on or outside of a channel side edge of the second region and contacting the channel region; the second region being of a higher impurity concentration than the first region in an area along a surface of the first source and the first drain regions under an edge of the first gate insulator layer; a P conductivity type region formed in the semiconductor surface portion; a second gate electrode formed on a second gate insulator layer formed on a surface of said P conductivity type region; a second channel region formed under said second gate insulator layer; and second source and second drain regions of N conductivity type, each of said second source and second drain regions including a high concentration N type region and a low concentration N type region, with edges of said high concentration N type region being more remote from the channel portion than edges of said low concentration N type region.

Claim 13

A P channel MIS type semiconductor device, comprising: a substrate having a semiconductor surface portion; an N conductivity type region formed in the semiconductor surface portion; a first gate insulator layer formed on the N conductivity type region; a first channel region formed under the first gate insulator layer; a first gate electrode formed on said first gate insulator layer; first source and first drain regions of P conductivity type with each having a same P-type impurity element and formed in the semiconductor surface region on opposite sides of the first channel region, each of said first source and first drain regions including first and second regions respectively, with said first region being of a higher impurity concentration than said second region in an area under each of a source and drain electrode formed on said first source and said first drain regions, respectively; a channel side edge of the first region arranged on or outside of a channel side edge of the second region and contacting the channel region; the second region being of a higher impurity concentration than the first region in an area along a surface of the first source and the first drain regions under an edge of the first gate insulator layer; a P conductivity type region formed in the semiconductor surface portion; a second gate electrode formed on a second gate insulator layer formed on a surface of said P conductivity type region; a second channel region formed under said second gate insulator layer; and second source and second drain regions of N conductivity type, each of said second source and second drain regions including a high concentration N type region and a low concentration N type region, with edges of said high concentration N type region being more remote from the channel portion than edges of said low concentration N type region.

Claim 14

The MIS type semiconductor device according to claim 11, further comprising: first source and first drain electrodes formed on a surface of said first source and first drain regions; and second source and second drain electrodes formed on a surface of said second source and second drain regions.

Claim 15

The MIS type semiconductor device according to claim 11, wherein one of said first source and first drain regions and one of said second source and second drain regions are electrically connected to each other, and said first and second gate electrodes are electrically connected to each other to form an inverter.

Claim 16

The MIS type semiconductor device according to claim 11, further comprising: side wall insulators being self aligned to said first and second gate electrodes; wherein said high concentration regions of said source and drain regions of both channel types are self-aligned to said gate electrodes and said side wall insulators, and said low concentration regions of said source and drain regions of both channel types are self-aligned to said gate electrodes.

Claim 17

The MIS type semiconductor device according to claim 11, wherein an impurity of said high and low concentration regions of said first source and first drain regions of said P type conductivity is boron, an impurity of said second source and second drain regions of said high concentration N type region is arsenic, and an impurity of said second source and second drain regions of said low concentration N type region is phosphorus.

Claim 18

The MIS type semiconductor device according to claim 11, wherein a bipolar transistor is formed on said substrate.

Claim 19

The MIS type semiconductor device according to claim 11, wherein said substrate is a semiconductor substrate, and said N conductivity type region and said P conductivity type region are formed in an epitaxial semiconductor layer formed on said semiconductor substrate.