US5163018A
Expired / Lapsed
US
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Digital signal processing circuit for carrying out a convolution computation using circulating coefficients
Assignee: Yamaha Corp
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Filing: 1991-01-22
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Granted: 1992-11-10
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Expires: 2011-01-22
Abstract
Abstract A digital signal processing circuit has a coefficient storing portion, a computing portion, a coefficient selection control portion and a coefficient transfer portion. The coefficient storing portion stores multiplier coefficients used for a convolution computation, in which a value of each multiplier coefficient can be arbitrarily changed. The computing portion stores a series of input data to be inputted thereto sequentially during certain period to be previously passed, so that the computing portion carries out the convolution computation on the series of input data by use of the multiplier coefficients. In addition, the coefficient selection control portion controls a selection of a data input/output manner, i.e., either a data first-in-first-out manner or a data circulation manner is selected. The coefficient transfer portion inputs the multiplier coefficients to the storing portion from a external device, or outputs the coefficients to the external device. The convolution computation is carried out on the series of input data by use of the multiplier coefficients, which are supplied from the coefficient storing portion or the coefficient transfer portion. Thus, various digital signal processings can be performed so that the large-scale convolution computation can be carried out on the series of input data by use of the multiplier coefficients which can be easily set.
Inventors
- 👤 Yuji Ikegaya
- 👤 Shinichi Muramatsu
- 👤 Yusuke Konagai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:02
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/15
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
186 words
A digital signal processing circuit for carrying out a convolution computation on a series of input data by use of a multiplier coefficient, comprising: (a) storing means for storing said multiplier coefficient, in which a value of each of a plurality of multiplier coefficients can be arbitrarily changed; (b) input/output control means for controlling a selection of a data input/output manner so that said multiplier coefficient is inputted to or outputted from said storing means by either a data first-in-first-out manner or a data circulation manner; (c) computing means for carrying out said convolution computation on said series of input data by use of said multiplier coefficient to be sequentially outputted from said storing means when said data circulation manner is selected; (d) output means for receiving the convolution computation from the computing means; and (e) coefficient transfer means coupled between the storing means and an external device for carrying out a transfer process on said multiplier coefficient, said coefficient transfer means being activated so that said multiplier coefficient is transferred between said storing means and the external device when said data first-in-first-out manner is selected.
Claim 2
Dependent Claim
186 words
A digital signal processing circuit for carrying out a convolution computation on a series of input data by use of a multiplier coefficient, comprising: (a) storing means for storing said multiplier coefficient, in which a value of each of a plurality of multiplier coefficients can be arbitrarily changed; (b) input/output control means for controlling a selection of a data input/output manner so that said multiplier coefficient is inputted to or outputted from said storing means by either a data first-in-first-out manner or a data circulation manner; (c) computing means for carrying out said convolution computation on said series of input data by use of said multiplier coefficient to be sequentially outputted from said storing means when said data circulation manner is selected; (d) output means for receiving the convolution computation from the computing means; and (e) coefficient transfer means coupled between the storing means and an external device for carrying out a transfer process on said multiplier coefficient, said coefficient transfer means being activated so that said multiplier coefficient is transferred between said storing means and the external device when said data first-in-first-out manner is selected.
Claim 3
Dependent Claim
68 words
A digital signal processing circuit according to claim 1, wherein said multiplier coefficient to be firstly inputted to said storing means is firstly outputted from said storing means in said data first-in-first-out manner, while said multiplier coefficients are repeatedly circulating through said storing means and a desirable one of them is picked up from said storing means during circulation of said multiplier coefficients in said data circulation manner.
Claim 4
Dependent Claim
25 words
A digital signal processing circuit according to claim 1, wherein said input data is inputted to said computing means sequentially during a predetermined sampling period.
Claim 5
Dependent Claim
44 words
A digital signal processing circuit according to claim 1, wherein said digital processing circuit comprises a plurality of units which comprise said storing means, input/output control means, computing means and coefficient transfer means, the plurality of units being connected together in a cascade manner.
Claim 6
Dependent Claim
189 words
A digital signal processing circuit for carrying out a convolution computation on a series of input data by use of a multiplier coefficient, comprising: (a) a shift register having a plurality of memory cells respectively storing said multiplier coefficient, said multiplier coefficient being sequentially shifted through said shift register in a data circulation manner; (b) selecting means for selecting plural memory cells from among the plurality of memory cells in said shift register, so that said multiplier coefficient is shifted through the selected plural memory cells in the data circulation manner; (c) computing means for carrying out a convolution computation on said series of input data by use of said multiplier coefficient to be sequentially picked up from a predetermined memory cell within the selected plural memory cells in the shift register; (d) output means for receiving the convolution computation from the computing means; (e) writing means for writing a multiplier coefficient supplied from an external device into a predetermined memory cell in the shift register; and (f) outputting means for outputting said multiplier coefficient stored in a predetermined memory cell in the shift register to said external device.
Claim 7
Dependent Claim
189 words
A digital signal processing circuit for carrying out a convolution computation on a series of input data by use of a multiplier coefficient, comprising: (a) a shift register having a plurality of memory cells respectively storing said multiplier coefficient, said multiplier coefficient being sequentially shifted through said shift register in a data circulation manner; (b) selecting means for selecting plural memory cells from among the plurality of memory cells in said shift register, so that said multiplier coefficient is shifted through the selected plural memory cells in the data circulation manner; (c) computing means for carrying out a convolution computation on said series of input data by use of said multiplier coefficient to be sequentially picked up from a predetermined memory cell within the selected plural memory cells in the shift register; (d) output means for receiving the convolution computation from the computing means; (e) writing means for writing a multiplier coefficient supplied from an external device into a predetermined memory cell in the shift register; and (f) outputting means for outputting said multiplier coefficient stored in a predetermined memory cell in the shift register to said external device.
Claim 8
Dependent Claim
21 words
A digital signal processing circuit according to claim 5, wherein each of the predetermined memory cells comprises the same memory cell.
Claim 9
Dependent Claim
21 words
A digital signal processing circuit according to claim 5, wherein two of the predetermined memory cells comprise the same memory cell.
Claim 10
Dependent Claim
180 words
A digital signal processing circuit for carrying out a convolution computation on a series of input data by use of multiplier coefficients, comprising: (a) a random access memory for storing a plurality of said multiplier coefficients; (b) input/output control means for controlling read/write addresses of said random access memory to thereby control a selection of a data input/output manner so that said plurality of multiplier coefficients are inputted to or outputted from said random access memory by either a data first-in-first-out manner or a data circulation manner; (c) computing means for carrying out a convolution computation on said series of input data by use of said plurality of multiplier coefficients to be sequentially circularly read from said random access memory; (d) output means for receiving the convolution computation from the computing means; and (e) coefficient transfer means for carrying out a transfer process on said plurality of multiplier coefficients, said coefficient transfer means being activated so that said plurality of multiplier coefficients are transferred between said random access memory and an external device when said data first-in-first-out manner is selected.
Claim 11
Dependent Claim
180 words
A digital signal processing circuit for carrying out a convolution computation on a series of input data by use of multiplier coefficients, comprising: (a) a random access memory for storing a plurality of said multiplier coefficients; (b) input/output control means for controlling read/write addresses of said random access memory to thereby control a selection of a data input/output manner so that said plurality of multiplier coefficients are inputted to or outputted from said random access memory by either a data first-in-first-out manner or a data circulation manner; (c) computing means for carrying out a convolution computation on said series of input data by use of said plurality of multiplier coefficients to be sequentially circularly read from said random access memory; (d) output means for receiving the convolution computation from the computing means; and (e) coefficient transfer means for carrying out a transfer process on said plurality of multiplier coefficients, said coefficient transfer means being activated so that said plurality of multiplier coefficients are transferred between said random access memory and an external device when said data first-in-first-out manner is selected.
Claim 12
Dependent Claim
81 words
A digital signal processing circuit according to claim 8, wherein that one of said plurality of multiplier coefficients to be firstly inputted to said random access memory is firstly outputted from said random access memory in said data first-in-first-out manner, while said plurality of multiplier coefficients are repeatedly circulating through said random access memory and a desirable one of them is picked up from said random access memory during circulation of said plurality of multiplier coefficients in said data circulation manner.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |