Sense amplifier for programmable logic device

Claim 2

For use with a linear array of programmable interconnection devices, said programmable interconnection devices sharing common drain and source lines and having individual gate lines, a sense amplifier for determining the interconnection state of said array, said sense amplifier comprising: a supply of fixed positive electrical potential; a supply of ground electrical potential; an output mode; first variable current limiting means connected between said output node and said supply of fixed positive potential; second variable current limiting means connected between said output node and said source line and being controlled by said drain line; third variable current limiting means connected between said source line and said supply of ground potential and being controlled by said drain line; and variable pull-up means for limiting potential on said drain line and for controlling said first variable current limiting means responsive to potential on said drain line; wherein: when none of said programmable interconnections is conducting, potential on said drain line is limited to a first positive potential less than said fixed positive potential, said first positive potential being sufficient to cause said second and third variable current limiting means to conduct, such that said source line and said output node are at ground potential; when only one of said programmable interconnections is conducting, potential on said drain line falls from said first positive potential to a second positive potential insufficient to cause said second variable current limiting means to conduct thereby isolating said output node from said supply of ground potential, said second positive potential being sufficient for said third variable current limiting means to conduct slightly, thereby causing potential on said source line to rise to a third positive potential as a result of potential drop across said third variable current limiting means caused by current flowing therethrough, said variable pull-up means responding to said second positive potential by causing said first variable current limiting means to conduct, thereby raising said output node to the potential of said supply of fixed positive potential; and as an increasing number of said programmable interconnections conducts, potential on said output node remains at said fixed positive potential and said drain and source lines approach a common potential above ground potential; whereby: at all times said drain line potential remains between said common potential and said first positive potential, limiting maximum possible change in potential on said drain line, thereby minimizing switching time of said sense amplifier.

Claim 3

The sense amplifier of claim 1 wherein each of said variable current limiting means comprises a transistor.

Claim 4

The sense amplifier of claim 2 wherein said transistor is a field effect transistor.

Claim 5

The sense amplifier of claim 3 wherein said first variable current limiting means comprises a p-channel field effect transistor.

Claim 6

The sense amplifier of claim 4 wherein said p-channel field effect transistor is in enhancement mode.

Claim 7

The sense amplifier of claim 3 wherein said second variable current limiting means comprises an n-channel field effect transistor.

Claim 8

The sense amplifier of claim 6 wherein said n-channel field effect transistor is in enhancement mode.

Claim 9

The sense amplifier of claim 3 wherein said third variable current limiting means comprises an n-channel field effect transistor.

Claim 10

The sense amplifier of claim 8 wherein said n-channel field effect transistor is in enhancement mode.

Claim 11

The sense amplifier of claim 1 wherein said variable pull-up means comprises cascode means connected between said drain line and said supply of fixed positive potential.

Claim 12

The sense amplifier of claim 10 wherein said cascode means comprises a transistor and a supply of reference potential connected to a control input of said transistor.

Claim 13

The sense amplifier of claim 11 wherein said cascode transistor is an n-channel field effect transistor and said control input is the gate of said field effect transistor.

Claim 14

The sense amplifier of claim 12 wherein said n-channel field effect transistor is in depletion mode.

Claim 15

The sense amplifier of claim 10 wherein said variable pull-up means further comprises a pull-up transistor connected between said cascode means and said supply of fixed positive potential, an output of said pull-up transistor configured to feed back to an input of said pull-up transistor, said output also connected to a control input of said first variable current limiting device.

Claim 16

The sense amplifier of claim 14 wherein said pull-up transistor is an n-channel field effect transistor with its gate connected to its source, to said cascode means and to said control input of said first variable current limiting device, and its drain connected to said supply of fixed positive potential.

Claim 17

The sense amplifier of claim 15 wherein said pull-up transistor is in depletion mode.

Claim 18

The sense amplifier of claim 1 wherein said programmable interconnection devices are EPROMs.

Claim 19

The sense amplifier of claim 17 wherein said EPROMs are EEPROMs.

Claim 20

The sense amplifier of claim 17 wherein said EPROMs are Flash EPROMs.

Claim 21

The sense amplifier of claim 1 further comprising an amplifier at said output node for producing an amplified output.

Claim 22

A programmable logic device comprising: a bit line conductor; a supply of ground electrical potential; a source line conductor; a plurality of word line conductors, each of which conducts an associated word line signal; a plurality of programmable interconnection devices, each of which, if programmed, is insensitive to the word line signal on a respective one of said word line conductors associated with said programmable interconnection device, and, if not programmed, is controlled by the word line signal on said respective associated word line to selectively connect said bit line conductor to said source line conductor; and a sense amplifier for determining the selective connection state of said programmable interconnection devices associated with said array; said sense amplifier comprising: a supply of fixed positive electrical potential; an output node; first variable current limiting means connected between said output node and said supply of fixed positive potential; second variable current limiting means connected between said output node and said source line and being controlled by said bit line; third variable current limiting means connected between said source line and said supply of ground potential and being controlled by said bit line; and variable pull-up means for limiting potential on said bit line and for controlling said first variable current limiting means responsive to potential on said bit line; wherein: when none of said programmable interconnections is conducting, potential on said bit line is limited to a first positive potential less than said fixed positive potential, said first positive potential being sufficient to cause said second and third variable current limiting means to conduct, such that said source line and said output node are at ground potential; when only one of said programmable interconnections is conducting, potential on said bit line falls from said first positive potential to a second positive potential insufficient to cause said second variable current limiting means to conduct thereby isolating said output node from said supply of ground potential, said second positive potential being sufficient for said third variable current limiting means to conduct slightly, thereby causing potential on said source line to rise to a third positive potential as a result of potential drop across said third variable current limiting means caused by current flowing therethrough, said variable pull-up means responding to said second positive potential by causing said first variable current limiting means to conduct, thereby raising said output node to the potential of said supply of fixed positive potential; and as an increasing number of said programmable interconnections conducts, potential on said output node remains at said fixed positive potential and said bit line and said source line approach a common potential above ground potential; whereby: at all times said bit line potential remains between said common potential and said first positive potential, limiting maximum possible change in potential on said bit line, thereby minimizing switching time of said sense amplifier.

Claim 23

A programmable logic device comprising: a bit line conductor; a supply of ground electrical potential; a source line conductor; a plurality of word line conductors, each of which conducts an associated word line signal; a plurality of programmable interconnection devices, each of which, if programmed, is insensitive to the word line signal on a respective one of said word line conductors associated with said programmable interconnection device, and, if not programmed, is controlled by the word line signal on said respective associated word line to selectively connect said bit line conductor to said source line conductor; and a sense amplifier for determining the selective connection state of said programmable interconnection devices associated with said array; said sense amplifier comprising: a supply of fixed positive electrical potential; an output node; first variable current limiting means connected between said output node and said supply of fixed positive potential; second variable current limiting means connected between said output node and said source line and being controlled by said bit line; third variable current limiting means connected between said source line and said supply of ground potential and being controlled by said bit line; and variable pull-up means for limiting potential on said bit line and for controlling said first variable current limiting means responsive to potential on said bit line; wherein: when none of said programmable interconnections is conducting, potential on said bit line is limited to a first positive potential less than said fixed positive potential, said first positive potential being sufficient to cause said second and third variable current limiting means to conduct, such that said source line and said output node are at ground potential; when only one of said programmable interconnections is conducting, potential on said bit line falls from said first positive potential to a second positive potential insufficient to cause said second variable current limiting means to conduct thereby isolating said output node from said supply of ground potential, said second positive potential being sufficient for said third variable current limiting means to conduct slightly, thereby causing potential on said source line to rise to a third positive potential as a result of potential drop across said third variable current limiting means caused by current flowing therethrough, said variable pull-up means responding to said second positive potential by causing said first variable current limiting means to conduct, thereby raising said output node to the potential of said supply of fixed positive potential; and as an increasing number of said programmable interconnections conducts, potential on said output node remains at said fixed positive potential and said bit line and said source line approach a common potential above ground potential; whereby: at all times said bit line potential remains between said common potential and said first positive potential, limiting maximum possible change in potential on said bit line, thereby minimizing switching time of said sense amplifier.

Claim 24

The programmable logic device of claim 21 wherein each of said variable current limiting means comprises a transistor.

Claim 25

The programmable logic device of claim 22 wherein said transistor is a field effect transistor.

Claim 26

The programmable logic device of claim 23 wherein said first variable current limiting means comprises a p-channel field effect transistor.

Claim 27

The programmable logic device of claim 24 wherein said p-channel field effect transistor is in enhancement mode.

Claim 28

The programmable logic device of claim 23 wherein said second variable current limiting means comprises an n-channel field effect transistor.

Claim 29

The programmable logic device of claim 26 wherein said n-channel field effect transistor is in enhancement mode.

Claim 30

The programmable logic device of claim 23 wherein said third variable current limiting means comprises an n-channel field effect transistor.

Claim 31

The programmable logic device of claim 28 wherein said n-channel field effect transistor is in enhancement mode.

Claim 32

The programmable logic device of claim 21 wherein said variable pull-up means comprises cascode means connected between said drain line and said supply of fixed positive potential.

Claim 33

The programmable logic device of claim 30 wherein said cascode means comprises a transistor and a supply of reference potential connected to a control input of said transistor.

Claim 34

The programmable logic device of claim 31 wherein said cascode transistor is an n-channel field effect transistor and said control input is the gate of said field effect transistor.

Claim 35

The programmable logic device of claim 32 wherein said n-channel field effect transistor is in depletion mode.

Claim 36

The programmable logic device of claim 30 wherein said variable pull-up means further comprises a pull-up transistor connected between said cascode means and said supply of fixed positive potential, an output of said pull-up transistor configured to feed back to an input of said pull-up transistor, said output also connected to a control input of said first variable current limiting device.

Claim 37

The programmable logic device of claim 34 wherein said pull-up transistor is an n-channel field effect transistor with its gate connected to its source, to said cascode means and to said control input of said first variable current limiting device, and its drain connected to said supply of fixed positive potential.

Claim 38

The programmable logic device of claim 35 wherein said pull-up transistor is in depletion mode.

Claim 39

The programmable logic device of claim 21 wherein said programmable interconnection devices are EPROMs.

Claim 40

The programmable logic device of claim 37 wherein said EPROMs are EEPROMs.

Claim 41

The programmable logic device of claim 37 wherein said EPROMs are Flash EPROMs.

Claim 42

The programmable logic device of claim 21 further comprising an amplifier at said output node for producing an amplified output.

Claim 43

For use with a linear array of programmable interconnection devices, said programmable interconnection devices sharing common drain and source lines and having individual gate lines, a sense amplifier for determining the interconnection state of said array, said sense amplifier comprising: a supply of fixed positive electrical potential; a supply of ground electrical potential; a supply of reference potential; an output node; a first enhancement mode n-channel field effect transistor having a source connected to said supply of ground potential, a drain connected to said source line, and a gate connected to said drain line; a second enhancement mode n-channel field effect transistor having a source connected to said source line, a drain connected to said output node, and a gate connected to said drain line; a cascode comprising a depletion mode n-channel field effect transistor having a source connected to said drain line and a gate connected to said supply of reference potential, and having a drain; a depletion mode n-channel field effect pull-up transistor having a drain connected to said supply of fixed positive potential and having a gate and a source, said gate being connected to said source; an enhancement mode p-channel field effect transistor having a source connected to said supply of fixed positive potential and a drain connected to said output node, and having a gate; and a pull-up node at which said drain of said cascode, said source of said pull-up transistor and said gate of said p-channel transistor are connected.

Claim 44

For use with a linear array of programmable interconnection devices, said programmable interconnection devices sharing common drain and source lines and having individual gate lines, a sense amplifier for determining the interconnection state of said array, said sense amplifier comprising: a supply of fixed positive electrical potential; a supply of ground electrical potential; a supply of reference potential; an output node; a first enhancement mode n-channel field effect transistor having a source connected to said supply of ground potential, a drain connected to said source line, and a gate connected to said drain line; a second enhancement mode n-channel field effect transistor having a source connected to said source line, a drain connected to said output node, and a gate connected to said drain line; a cascode comprising a depletion mode n-channel field effect transistor having a source connected to said drain line and a gate connected to said supply of reference potential, and having a drain; a depletion mode n-channel field effect pull-up transistor having a drain connected to said supply of fixed positive potential and having a gate and a source, said gate being connected to said source; an enhancement mode p-channel field effect transistor having a source connected to said supply of fixed positive potential and a drain connected to said output node, and having a gate; and a pull-up node at which said drain of said cascode, said source of said pull-up transistor and said gate of said p-channel transistor are connected.

Claim 45

The sense amplifier of claim 41 further comprising an amplifier at said output node for producing an amplified output.