US5161229A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Central processing unit
Assignee: Ricoh Co Ltd
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Filing: 1990-06-05
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Granted: 1992-11-03
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Expires: 2010-06-05
Abstract
Abstract A central processing unit has a plurality of control sections; a device for selectively operating and unoperating the control sections by an external interrruption signal; and a device for processing an interruption sequence with respect to the interruption signal by the operations of the control sections in a state in which the control sections are operated. The control processing unit may be constructed such that the control sections are composed of two control sections and one of the two control sections processes a normal instruction sequence and is unoperated by the interruption signal, and the other of the two control sections is operated at the times of the normal instruction and interruption and processes the interruption sequence in addition to the normal instruction.
Inventors
- 👤 Takashi Yasui
- 👤 Keiichi Yoshioka
- 👤 Shinichi Yamaura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
186 words
A central processing unit comprising: an arithmetic circuit for performing an arithmetic processing; an interruption control circuit for outputting an interruption control signal for an interruption processing on the basis of an external interruption signal inputted thereto; a first control means connected to said interruption control circuit and said arithmetic circuit for controlling operations of said arithmetic circuit so as to cause said arithmetic circuit to perform the arithmetic processing when said first control means does not receive the interruption control signal from said interruption control circuit and to prevent a performing of the arithmetic processing when said first control means receives the interruption control signal from said interruption control circuit; and a second control means connected to said interruption control circuit and said arithmetic circuit for controlling operations of said arithmetic circuit so as to cause said arithmetic circuit to perform the interruption processing when said second control means receives the interruption control signal from said interruption control circuit and to prevent a performing of the interruption processing when said second control means does not receive the interruption control signal from said interruption control circuit.
Claim 2
Dependent Claim
186 words
A central processing unit comprising: an arithmetic circuit for performing an arithmetic processing; an interruption control circuit for outputting an interruption control signal for an interruption processing on the basis of an external interruption signal inputted thereto; a first control means connected to said interruption control circuit and said arithmetic circuit for controlling operations of said arithmetic circuit so as to cause said arithmetic circuit to perform the arithmetic processing when said first control means does not receive the interruption control signal from said interruption control circuit and to prevent a performing of the arithmetic processing when said first control means receives the interruption control signal from said interruption control circuit; and a second control means connected to said interruption control circuit and said arithmetic circuit for controlling operations of said arithmetic circuit so as to cause said arithmetic circuit to perform the interruption processing when said second control means receives the interruption control signal from said interruption control circuit and to prevent a performing of the interruption processing when said second control means does not receive the interruption control signal from said interruption control circuit.
Claim 3
Dependent Claim
23 words
A central processing unit according to claim 1, in which said first control means and said second control means each include respective decoders.
References Cited (Backward Citations)
US4003028A
Cited
US4037204A
Cited
US4001783A
Cited
US4160289A
Cited
US4128739A
Cited
US4422141A
Cited
US4517643A
Cited
US4969119A
Cited
US4975839A
Cited
US4998197A
Cited
US4912628A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |