US5159705A
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Frequency synthesizer circuit
Assignee: InterDigital Technology Corp
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Filing: 1992-03-13
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Granted: 1992-10-27
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Expires: 2012-03-13
Abstract
Abstract A frequency synthesizer that generates two output signals at a set frequency apart from each other and in synchronization with each other. The output frequency is selected by a microprocessor and the set frequency difference between the two output signals is determined by a frequency divider and a voltage controlled oscillator.
Inventors
- 👤 David N. Critchlow
- 👤 Graham M. Avis
- 👤 Sandra J. K. Earlam
- 👤 Karle J. Johnson
- 👤 Bruce A. Smetana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:22
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/72; H04M1/725; H04M1/72502; H04M11/00; H04M11/06; H03; H03D; H03D3/00; H03D3/006; H03D7/00; H03D7/16; H03D7/165; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0621; H03H17/0635; H03H17/065; H03H17/0657; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H04B; H04B1/00; H04B1/38; H04B1/40; H04B1/50; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/144; H04L27/152; H04L27/1525; H04L27/18; H04L27/22; H04L27/233; H04L27/2338; H03D2200/00; H03D2200/0041; H03D2200/005; H03D2200/0052; H03D2200/0054; H03D2200/0058; H03D2200/006; H03D2200/0062; H03D2200/0082; H03D3/007; H03D7/161
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
147 words
a frequency synthesizer circuit comprising: oscillator means that outputs a synchronizing signal; means for generating a control input signal; a synthesizer unit having a first input which receives the synchronizing signal, a second input which receives the control input signal and an output, wherein the synthesizer unit, in response to the control input signal, generates, at the output, a synthesizer output signal which is in synchronism with the synchronizing signal; a frequency dividing means which receives the synchronizing signal, as output by the oscillator, divides it by a predetermined value and outputs a divided synchronizing signal; and a mixing means which mixes the synthesizer output signal with the divided synchronizing signal and generates a second synthesizer output signal which is in synchronism with the first output signal but has a frequency which is lower than the first output signal by the value of the divided synchronizing signal.
Claim 2
Dependent Claim
147 words
a frequency synthesizer circuit comprising: oscillator means that outputs a synchronizing signal; means for generating a control input signal; a synthesizer unit having a first input which receives the synchronizing signal, a second input which receives the control input signal and an output, wherein the synthesizer unit, in response to the control input signal, generates, at the output, a synthesizer output signal which is in synchronism with the synchronizing signal; a frequency dividing means which receives the synchronizing signal, as output by the oscillator, divides it by a predetermined value and outputs a divided synchronizing signal; and a mixing means which mixes the synthesizer output signal with the divided synchronizing signal and generates a second synthesizer output signal which is in synchronism with the first output signal but has a frequency which is lower than the first output signal by the value of the divided synchronizing signal.
Claim 3
Dependent Claim
28 words
The frequency synthesizer circuit of claim 1 wherein the synthesizer unit includes a read only memory to store information which determines the frequency of the synthesizer output signal.
Claim 4
Dependent Claim
19 words
A frequency synthesizer circuit of claim 1, wherein the means for generating a control input signal is a microprocessor.
Claim 5
Dependent Claim
31 words
The frequency synthesizer circuit of claim 1, further including a synthesizer filter means for filtering the first output signal and a second filtering means for filtering the second synthesizer output signal.
Claim 6
Dependent Claim
23 words
The frequency synthesizer circuit of claim 1 wherein the oscillator means includes an adjustment input for controlling the frequency of the synchronizing signal.
Claim 7
Dependent Claim
46 words
The frequency synthesizer circuit of claim 1 further including a synchronization detector which receives the synthesizer output signal from the synthesizer unit and the second synthesizer output signal from the mixing means, and upon detection of a loss of phase synchronization outputs a lock loss signal.
Claim 8
Dependent Claim
104 words
A dual-frequency synthesizer circuit comprising: means for generating a synchronizing signal; means for generating a control input signal; synthesizing means for receiving the control input signal and the synchronizing signal, and providing a first output signal in response thereto; frequency dividing means for receiving the synchronizing signal, dividing it by a predetermined value, and outputting a divided synchronizing signal; and a synchronous translator for mixing the first output signal with the divided synchronizing signal to provide a second output signal which is in synchronism with the first output signal and has a frequency which differs from the first output signal by a set value.
Claim 9
Dependent Claim
104 words
A dual-frequency synthesizer circuit comprising: means for generating a synchronizing signal; means for generating a control input signal; synthesizing means for receiving the control input signal and the synchronizing signal, and providing a first output signal in response thereto; frequency dividing means for receiving the synchronizing signal, dividing it by a predetermined value, and outputting a divided synchronizing signal; and a synchronous translator for mixing the first output signal with the divided synchronizing signal to provide a second output signal which is in synchronism with the first output signal and has a frequency which differs from the first output signal by a set value.
Claim 10
Dependent Claim
19 words
The dual-frequency synthesizer circuit of claim 7 wherein the means for generating a control input signal is a microprocessor.
Claim 11
Dependent Claim
28 words
The dual-frequency synthesizer circuit of claim 8 wherein the synthesizing means includes a read only memory to store information which determines the frequency of the first output signal.
Claim 12
Dependent Claim
49 words
The dual frequency synthesizer circuit of claim 9 further comprising a synchronization detector which receives the first output signal from the synthesizing means and the second output signal from the synchronous translator, and upon detection of a loss of synchronization outputs a loss of synchronization signal to the microprocessor.
Claim 13
Dependent Claim
130 words
A dual-frequency synthesizer circuit comprising: an oscillator for generating a synchronizing signal, the output of said oscillator is inputted to a synthesizing means and a frequency dividing means, whereby the frequency dividing means divides the synchronizing signal by a predetermined value; means for generating a control input signal, having an output which is inputted to the synthesizing means, whereby the synthesizing means generates a first output signal in response to the synchronizing signal and the control input signal, wherein the first output signal is in phase with the synchronizing signal; and a synchronous translator for mixing the first output signal with the divided synchronizing signal to generate a second output signal which is in phase with the first output signal, but at a frequency different than the first output signal.
Claim 14
Dependent Claim
130 words
A dual-frequency synthesizer circuit comprising: an oscillator for generating a synchronizing signal, the output of said oscillator is inputted to a synthesizing means and a frequency dividing means, whereby the frequency dividing means divides the synchronizing signal by a predetermined value; means for generating a control input signal, having an output which is inputted to the synthesizing means, whereby the synthesizing means generates a first output signal in response to the synchronizing signal and the control input signal, wherein the first output signal is in phase with the synchronizing signal; and a synchronous translator for mixing the first output signal with the divided synchronizing signal to generate a second output signal which is in phase with the first output signal, but at a frequency different than the first output signal.
Claim 15
Dependent Claim
17 words
The dual-frequency synthesizer circuit of claim 11 wherein the control input signal generating means is a microprocessor.
Claim 16
Dependent Claim
28 words
The dual-frequency synthesizer circuit of claim 12 wherein the synthesizing means includes a read only memory to store information which determines the frequency of the first output signal.
Claim 17
Dependent Claim
48 words
The dual-frequency synthesizer circuit of claim 13 further comprising a synchronization detector which receives the first output signal from the synthesizing means and the second output signal from the synchronous translator, and upon detection of a loss of phase synchronization outputs a lock loss signal to the microprocessor.
Claim 18
Dependent Claim
30 words
The dual-frequency synthesizer circuit of claim 11 further comprising a first filter means for filtering the first output signal and a second filtering means for filtering the second output signal.
Claim 19
Dependent Claim
24 words
The frequency synthesizer circuit of claim 11 further comprising an adjustment means connected to the oscillator for controlling the frequency of the synchronizing signal.
Claim 20
Independent Claim
87 words
A method for generating two frequencies which are synchronous with each other comprising the steps of: generating a synchronizing signal; generating a control input signal; synthesizing a first output signal in response to the synchronizing signal and the control input signal; dividing the synchronizing signal by a predetermined value; and mixing the divided synchronizing signal with the first output signal to produce a second output signal at a frequency different from the first output signal by a set frequency and in synchronism with the first output signal.
Claim 21
Independent Claim
87 words
A method for generating two frequencies which are synchronous with each other comprising the steps of: generating a synchronizing signal; generating a control input signal; synthesizing a first output signal in response to the synchronizing signal and the control input signal; dividing the synchronizing signal by a predetermined value; and mixing the divided synchronizing signal with the first output signal to produce a second output signal at a frequency different from the first output signal by a set frequency and in synchronism with the first output signal.
Claim 22
Dependent Claim
42 words
The method of claim 17 wherein said method further includes the steps of comparing the first output signal with the second output signal and generating a lock loss signal upon the detection of the loss of synchronization between the two output signals.
Claim 23
Dependent Claim
131 words
A frequency synthesizer circuit comprising: oscillator means that outputs a synchronizing signal; means for generating a control input signal; a synthesizer unit having a first input which receives the synchronizing signal, a second input which receives the control input signal and an output, wherein the synthesizer unit, in response to the control input signal, generates, at the output, a synthesizer output signal which is in synchronism with the synchronizing signal; frequency dividing means which receives the synchronizing signal, as output by the oscillator, divides it by a predetermined value and outputs a divided synchronizing signal; and mixing means which mixes the synthesizer output signal with the divided synchronizing signal and generates a second synthesizer output signal which is in synchronism with but at a different frequency than the first output signal.
Claim 24
Dependent Claim
131 words
A frequency synthesizer circuit comprising: oscillator means that outputs a synchronizing signal; means for generating a control input signal; a synthesizer unit having a first input which receives the synchronizing signal, a second input which receives the control input signal and an output, wherein the synthesizer unit, in response to the control input signal, generates, at the output, a synthesizer output signal which is in synchronism with the synchronizing signal; frequency dividing means which receives the synchronizing signal, as output by the oscillator, divides it by a predetermined value and outputs a divided synchronizing signal; and mixing means which mixes the synthesizer output signal with the divided synchronizing signal and generates a second synthesizer output signal which is in synchronism with but at a different frequency than the first output signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-27 | 1996-04-27 | 1996-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-27 | 2000-04-27 | 2000-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-27 | 2004-04-27 | 2004-10-27 | $7700.00 | Window Closed / Lapsed |