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US5159673A Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus for networking programmable logic controllers to host computers

Assignee: Schneider Electric USA Inc
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Filing: 1992-03-11
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Granted: 1992-10-27
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Expires: 2012-03-11
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Abstract

Abstract A control system allows for transferring messages between a programmable logic controller and a host computer over an Ethernet communications network. The messages include a routing address specifying an originating drop number, a destination drop number, and a routing drop number. The system is responsive to the routing address for transferring the messages between the programmable logic controller and the host computer. The host computer can immediately obtain messages from a programmable logic controller without interruption of the execution of its ladder program. The host computer can also receive unsolicited messages from the programmable logic controller.

Inventors

  • 👤 David J. Sackmann
  • 👤 Brian T. Hill
  • 👤 Joseph T. Bronikowski
  • 👤 Mark S. Weber

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 22:50
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/052; H; H04; H04L; H04L51/00; H04L51/21; H04L51/212; H04L51/48; H04L9/00; H04L9/40

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 408 words
A control system for transferring messages between microprocessor based devices connected to a high speed serial data communications network comprising: (a) a programmable logic controller including (b) a communications processor coupled to said communications network for sending and receiving said messages, (c) a two-port RAM (random access memory) having a first port connected to said communications processor and having means for receiving and temporarily storing messages from said communication processor said RAM having a second port, (d) a data bus coupled to the second port of the RAM, (e) a scan processor means coupled to said data bus for executing a ladder program, (f) an image table means coupled to said data bus for storing said messages accessible by said scan processor through said data bus, (g) a control processor means coupled to said image table and to said scan processor and connected to the second port of said two-port RAM via said data bus for transferring said messages between said image table and said two-port RAM, (h) said control processor having means for reading and writing said messages from and to said second port of the two-port RAM at one predetermined time, and (i) said communications processor having means for reading and writing said messages from and to said first port of the two-port RAM independent from said means of said control processor at a second predetermined time; (j) a host computer coupled to said network, said host computer including (k) a microprocessor having a system task memory and a plurality of user task memories, said microprocessor having means for executing the system task and the plurality of user tasks, respectively, said system task and said plurality of user tasks including means for sending and receiving said messages on said communications network, (l) a dispatcher means coupled between the system task memory and the user task memories and said communications network for controlling said message transfers between said system task memory and said user task memories and said other microprocessor based devices connected to said communications network independent of the execution of said user tasks by said microprocessor; (m) wherein said host computer can send to and receive from said programmable logic controller said messages immediately independent of the execution of the ladder program by said scan processor; and (n) wherein said programmable logic controller can obtain messages directly from said user tasks in the host computer while said user tasks are executing in said host computer.
Claim 2
Dependent Claim 408 words
A control system for transferring messages between microprocessor based devices connected to a high speed serial data communications network comprising: (a) a programmable logic controller including (b) a communications processor coupled to said communications network for sending and receiving said messages, (c) a two-port RAM (random access memory) having a first port connected to said communications processor and having means for receiving and temporarily storing messages from said communication processor said RAM having a second port, (d) a data bus coupled to the second port of the RAM, (e) a scan processor means coupled to said data bus for executing a ladder program, (f) an image table means coupled to said data bus for storing said messages accessible by said scan processor through said data bus, (g) a control processor means coupled to said image table and to said scan processor and connected to the second port of said two-port RAM via said data bus for transferring said messages between said image table and said two-port RAM, (h) said control processor having means for reading and writing said messages from and to said second port of the two-port RAM at one predetermined time, and (i) said communications processor having means for reading and writing said messages from and to said first port of the two-port RAM independent from said means of said control processor at a second predetermined time; (j) a host computer coupled to said network, said host computer including (k) a microprocessor having a system task memory and a plurality of user task memories, said microprocessor having means for executing the system task and the plurality of user tasks, respectively, said system task and said plurality of user tasks including means for sending and receiving said messages on said communications network, (l) a dispatcher means coupled between the system task memory and the user task memories and said communications network for controlling said message transfers between said system task memory and said user task memories and said other microprocessor based devices connected to said communications network independent of the execution of said user tasks by said microprocessor; (m) wherein said host computer can send to and receive from said programmable logic controller said messages immediately independent of the execution of the ladder program by said scan processor; and (n) wherein said programmable logic controller can obtain messages directly from said user tasks in the host computer while said user tasks are executing in said host computer.
Claim 3
Dependent Claim 17 words
The control system of claim 1 wherein said high speed data communications network is an Ethernet network.
Claim 4
Dependent Claim 33 words
The control system of claim 1 wherein each of said plurality of user tasks memories includes means for receiving unsolicited ones of said messages from said programmable logic controller via said communications network.
Claim 5
Dependent Claim 51 words
The control system of claim 3 wherein said system task memory included in said host computer includes a a global mailbox register associated with said system task memory, and means for receiving unsolicited ones of said messages from said programmable logic controller directed to said global mailbox via said communications network.
Claim 6
Dependent Claim 14 words
The control system of claim 1 wherein said host computer comprises a VAX computer.

References Cited (Backward Citations)

US4271507A Cited
US4482982A Cited
US4412285A Cited
US4672570A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-10-27 1996-04-27 1996-10-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-10-27 2000-04-27 2000-10-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-10-27 2004-04-27 2004-10-27 $7700.00 Window Closed / Lapsed

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