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US5159282A Expired / Lapsed US ⏱️ 0.0 years remaining

Demodulation apparatus incorporating adaptive equalizer for digital communication

Assignee: Toshiba Corp
•
Filing: 1990-12-06
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Granted: 1992-10-27
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Expires: 2010-12-06
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Abstract

Abstract A demodulation apparatus incorporating an adaptive equalizer, capable of realizing a highly reliable communication, lower power consumption, and a compact size. In the demodulation apparatus, an output of one of two demodulators, at least one of which including an equalizer, is selected according to a presence or absence of multipath which is determined from a non-coincidence of bit codes, eye apertures, bit error rates, or a matched filter output, while the operation of the other demodulator is stopped for reduction of power consumption, by stopping a supply of power or clock signals to the other demodulator. In a case using a frequency offset detection unit and a frequency offset memory, one of these is selected according to a convergence or divergence of an error signal from an equalizer, while the operation of the other one is stopped for reduction of power consumption.

Inventors

  • 👤 Mutsumu Serizawa
  • 👤 Minoru Namekata
  • 👤 Koji Ogura
  • 👤 Katsumi Sakakibara

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 06:51
CPC Classifications
H; H04; H04L; H04L27/00; H04L1/00; H04L1/0001; H04L1/20; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 94 words
A demodulation apparatus, comprising: a distributor for distributing an input signal to a first and a second passages; a first demodulator including an equalizer capable of compensating a transmission path distortion, connected with the first passage, for demodulating the input signal; a second demodulator, connected with the second passage, for demodulating the input signal; means for measuring a rate of non-coincidence between bit codes of outputs of the first and second demodulators; and means for selectively outputting one of the outputs of the first and second demodulators according to the measured rate of non-coincidence.
Claim 2
Dependent Claim 94 words
A demodulation apparatus, comprising: a distributor for distributing an input signal to a first and a second passages; a first demodulator including an equalizer capable of compensating a transmission path distortion, connected with the first passage, for demodulating the input signal; a second demodulator, connected with the second passage, for demodulating the input signal; means for measuring a rate of non-coincidence between bit codes of outputs of the first and second demodulators; and means for selectively outputting one of the outputs of the first and second demodulators according to the measured rate of non-coincidence.
Claim 3
Dependent Claim 38 words
The apparatus of claim 1, wherein the selectively outputting means outputs an output of the first demodulator when the measured rate of non-coincidence is greater than a prescribed threshold value, and an output of the second demodulator otherwise.
Claim 4
Dependent Claim 37 words
The apparatus of claim 1, further comprising means for stopping, for a prescribed period of time, a power supply to one of the first and second demodulators whose output is not selected by the selectively outputting means.
Claim 5
Dependent Claim 38 words
The apparatus of claim 1, further comprising means for stopping, for a prescribed period of time, a clock signal supply to one of the first and second demodulators whose output is not selected by the selectively outputting means.
Claim 6
Dependent Claim 13 words
The apparatus of claim 1, wherein the second demodulator includes a delay detector.
Claim 7
Dependent Claim 27 words
The apparatus of claim 1, wherein the second demodulator includes another equalizer which has a equalization characteristic different from that of the equalizer of the first demodulator.

References Cited (Backward Citations)

US4246541A Cited
JPS6351737A Cited
JPS648750A Cited
US4859957A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-10-27 1996-04-27 1996-10-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-10-27 2000-04-27 2000-10-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-10-27 2004-04-27 2004-10-27 $7700.00 Window Closed / Lapsed

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