US5157664A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tester for semiconductor memory devices
Assignee: Texas Instruments Inc
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Filing: 1989-09-21
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Granted: 1992-10-20
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Expires: 2009-09-21
Abstract
Abstract An offline redundancy memory test system replaces fail memory equipment, under the control of a test system CPU, with fail memory equipment under the control of a second CPU. The second CPU is dedicated to the analysis of the contents of the offline redundancy memory test system fail memory, for redundancy identification and defect pattern analysis, at the conclusion of functional testing. Therefore, in a mass production wafer level memory test system, the test system CPU is free to prepare and execute non-functional tests on the next set of devices to be tested, thereby reducing overall memory test time by the amount of fail memory equipment analysis time previously taken by the test system CPU leading to a reduction in the total number of memory test systems required to provide redundancy memory testing.
Inventors
- 👤 Harold C. Waite
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/72; G11C29/56; G06; G06F; G06F11/00; G06F11/22; G06F11/2205
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
163 words
A test system providing repair information for a semiconductor memory device of the type having addressable storage cells and redundant row or column lines of storage cells for replacing defective cells, comprising: a first subsystem including a first microprocessor and pattern generating circuitry operable in conjunction with a probe unit to write binary values based on a test pattern to addressed cells in the memory device and read binary values stored in the memory device; comparator circuitry coupled to the first subsystem for providing information identifying defective cells in the memory device based on differences between the binary values written into and read out of the addressed cells. a fail memory coupled to the comparator circuitry for storing the information identifying the defective cells; a second subsystem including a second microprocessor coupled to read the information from the fail memory said second subsystem designating a column or row line for replacement with a redundant line to correct a defect in the memory device.
Claim 2
Dependent Claim
163 words
A test system providing repair information for a semiconductor memory device of the type having addressable storage cells and redundant row or column lines of storage cells for replacing defective cells, comprising: a first subsystem including a first microprocessor and pattern generating circuitry operable in conjunction with a probe unit to write binary values based on a test pattern to addressed cells in the memory device and read binary values stored in the memory device; comparator circuitry coupled to the first subsystem for providing information identifying defective cells in the memory device based on differences between the binary values written into and read out of the addressed cells. a fail memory coupled to the comparator circuitry for storing the information identifying the defective cells; a second subsystem including a second microprocessor coupled to read the information from the fail memory said second subsystem designating a column or row line for replacement with a redundant line to correct a defect in the memory device.
Claim 3
Dependent Claim
26 words
The system of claim 1 wherein the comparator circuitry is formed as part of the first subsystem and is under the control of the first microprocessor.
Claim 4
Dependent Claim
11 words
The system of claim 1 wherein the fail memory comprises SRAM.
Claim 5
Dependent Claim
14 words
The system of claim 1 wherein the fail memory comprises 16 megabits of SRAM.
Claim 6
Independent Claim
161 words
A method for testing and providing repair information for a first memory device of the type having addressable storage cells and redundant row or column lines of storage cells for replacing defective cells, the method comprising the steps of: generating a test pattern for evaluating operation of the memory device; writing the test pattern based on binary data into addressed storage cells of the memory device with a first microprocessor; reading data stored in the addressed cells; providing information identifying defective cells in the memory device by comparing the binary values written into addressed cells with binary values read out of the addressed cells; storing the information in a fail memory device; reading the information from the fail memory device with a second microprocessor; and operating on the information with the second microprocessor to determine a repair pattern according to which a column or row line can be replaced with a redundant line to eliminate a defect in the memory device.
Claim 7
Independent Claim
161 words
A method for testing and providing repair information for a first memory device of the type having addressable storage cells and redundant row or column lines of storage cells for replacing defective cells, the method comprising the steps of: generating a test pattern for evaluating operation of the memory device; writing the test pattern based on binary data into addressed storage cells of the memory device with a first microprocessor; reading data stored in the addressed cells; providing information identifying defective cells in the memory device by comparing the binary values written into addressed cells with binary values read out of the addressed cells; storing the information in a fail memory device; reading the information from the fail memory device with a second microprocessor; and operating on the information with the second microprocessor to determine a repair pattern according to which a column or row line can be replaced with a redundant line to eliminate a defect in the memory device.
Claim 8
Dependent Claim
22 words
The method of claim 5 wherein the step of reading data stored in the addressed cells is performed with the first microprocessor.
Claim 9
Dependent Claim
23 words
The method of claim 5 wherein the step of storing the information in the fail memory device is performed with the first microprocessor.
Claim 10
Dependent Claim
78 words
The method of claim 5 further comprising the following steps at least one of which is performed while the second microprocessor operates on the information identifying defective cells in the first memory device: generating a test pattern for evaluating operation of a second memory device; writing the test pattern based on binary data into addressed storage cells of the second memory device with the first microprocessor; and reading data stored in the addressed cells of the second device.
Claim 11
Dependent Claim
21 words
The method of claim 5 further including the step of performing software defect analysis on the information with the second microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |