← Back to Patent Explorer
US5155779A Expired / Lapsed US ⏱️ 0.0 years remaining

Optical circulating shift register

Assignee: Nokia Bell Labs
•
Filing: 1991-11-05
•
Granted: 1992-10-13
•
Expires: 2011-11-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An all-optical circulating shift register encodes a received optical clock signal with a value derived from an encoded optical signal received at a control port thereof. A data input to the shift register is used to modify an encoded optical signal. The resulting encoded clock signal, appearing at an output port, is coupled back to the control port. The shift register uses the encoded clock signal at the control port to encode a subsequently-received clock signal. In one embodiment, the optical shift register is implemented using a Sagnac switch having a feedback path coupled between an output port and a control port of the Sagnac switch.

Inventors

  • 👤 Hercules Avramopoulos
  • 👤 M. Christina Gabriel
  • 👤 Alan Huang
  • 👤 Norman A. Whitaker, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 06:15
CPC Classifications
G; G11; G11C; G11C21/00; G02; G02B; G02B6/00; G02B6/24; G02B6/26; G02B6/28; G02B6/2804; G02B6/2821; G02B6/2843

Claims Analysis

Total Claims: 30
Claim 1
Independent Claim 90 words
A circulating shift resister arrangement comprising: encoding means utilizing all-optical interaction, including means for receiving an optical clock signal, control means for receiving an encoded optical signal, means for outputting an encoded optical clock signal, wherein said encoding means encodes the received clock signal with a value derived from said encoded signal, and wherein a signal delay caused by said encoding means from said control means to said output means is a prespecified time interval; means for coupling the encoded clock signal from said output means to said control means.
Claim 2
Dependent Claim 90 words
A circulating shift resister arrangement comprising: encoding means utilizing all-optical interaction, including means for receiving an optical clock signal, control means for receiving an encoded optical signal, means for outputting an encoded optical clock signal, wherein said encoding means encodes the received clock signal with a value derived from said encoded signal, and wherein a signal delay caused by said encoding means from said control means to said output means is a prespecified time interval; means for coupling the encoded clock signal from said output means to said control means.
Claim 3
Dependent Claim 16 words
The shift register arrangement of claim 1 wherein said all-optical interaction includes a nonlinear optical process.
Claim 4
Dependent Claim 23 words
The shift register arrangement of claim 1 further comprising means for entering data into the shift register to modify the encoded clock signal.
Claim 5
Dependent Claim 22 words
The shift register arrangement of claim 1 further comprising means for modulating said clock signal in response to a received data signal.
Claim 6
Dependent Claim 26 words
The shift register arrangement of claim 1 wherein the coupling means includes means for modulating the encoded clock signal in response to a received data signal.
Claim 7
Dependent Claim 20 words
The shift register arrangement of claim 1 further comprising means for inputting a received data signal into said control means.
Claim 8
Dependent Claim 17 words
The shift register arrangement of claim 6 wherein said received data signal is a plurality of pulses.
Claim 9
Dependent Claim 37 words
The shift register arrangement of claim 7 wherein said clock signal is a plurality of pulses and wherein the pulse rate of said clock signal and the pulse rate of said received data signal are substantially synchronized.
Claim 10
Dependent Claim 16 words
The shift register arrangement of claim 1 wherein said clock signal is a plurality of pulses.
Claim 11
Dependent Claim 28 words
The shift register arrangement of claim 9 wherein the time interval between two or more pulses of said clock signal are substantially equal to said prespecified time interval.
Claim 12
Dependent Claim 28 words
The shift register arrangement of claim 1 wherein said encoding means includes a second control means for inputting a received data signal for modulating the encoded clock signal.
Claim 13
Dependent Claim 17 words
The shift register arrangement of claim 11 wherein said received data signal is a plurality of pulses.
Claim 14
Dependent Claim 199 words
The shift register arrangement of claim 1 wherein said encoding means includes a Sagnac switch including an optical transmission medium having a controllable propagation speed characteristic; input port means for serially injecting said clock signal into said medium to develop an interacting signal that travels in said medium in one direction and a reference signal that travels in said medium in the opposite direction; control port means for injecting a control signal into said medium, said control signal travels through said medium in the direction of said interacting signal, with the timing of said control signal, in relation to said interacting signal, controlled to traverse the control signal by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means for generating a combined signal by combining said interacting signal with said reference signal after said signals have traveled through said medium; output port means for outputting said combined signal; and wherein said receiving means is coupled to said input port of said Sagnac switch, said control means is coupled to said control port of said Sagnac switch, and said coupling means couples an output port of said Sagnac switch to said control port.
Claim 15
Dependent Claim 17 words
The shift register arrangement of claim 13 wherein said medium includes an even number of crossed-axis splices.
Claim 16
Dependent Claim 22 words
The shift register arrangement of claim 13 wherein said output port outputs a combined signal in the absence of said control signal.
Claim 17
Dependent Claim 21 words
The shift register arrangement of claim 13 wherein said output port outputs a combined signal when said control signal is present.
Claim 18
Dependent Claim 25 words
The shift register arrangement of claim 1 wherein said output port alternately outputs said encoded clock signal and an inverse of said encoded clock signal.
Claim 19
Dependent Claim 22 words
The shift register arrangement of claim 1 wherein said coupling means includes a feedback path having an optical amplifier connected serially therein.
Claim 20
Dependent Claim 16 words
The shift register arrangement of claim 18 wherein said optical amplifier is an erbium-doped fiber amplifier.
Claim 21
Dependent Claim 25 words
The shift register arrangement of claim 1 wherein said coupling means includes a feedback path causing a predetermined time delay to said encoded clock signal.
Claim 22
Dependent Claim 52 words
The shift register arrangement or claim 20 wherein said clock signal includes a plurality of pulses, wherein said feedback path causes a predetermined time delay to said encode clock signal and wherein said predetermined time delay together with said prespecified time delay enable is sufficient to hold said plurality of clock pulses.
Claim 23
Dependent Claim 54 words
The shift register arrangement of claim 1 wherein said encoding means includes a Sagnac switch and wherein said receiving means is an input port of said Sagnac switch; said control means is a control port of said Sagnac switch; and said coupling means couples an output of said Sagnac switch to said control port.
Claim 24
Dependent Claim 53 words
The shift register arrangement of claim 1, further comprising means for inputting a probe signal to said encoding means, means for outputting an encoded probe signal from said encoding means, and wherein said encoding means encodes the probe signal with a value derived from said encoded signal to produce said encoded probe signal.
Claim 25
Dependent Claim 24 words
The shift register arrangement of claim 23 wherein said probe signal is an optical pulse which is substantially synchronized with said optical clock signal.
Claim 26
Dependent Claim 43 words
The shift register arrangement of claim 24 wherein the probe signal includes a plurality of pulses at a first pulse rate and said clock signal includes a plurality of pulses at a second pulse rate which is greater than said first pulse rate.
Claim 27
Dependent Claim 222 words
An optical circuit arrangement comprising an optical transmission medium including controllable propagation speed material; input port means for injecting optical clock pulses into said medium to develop, for each clock pulse, an interacting signal that travels in said medium in one direction and an associated reference signal that travels in said medium in the opposite direction; control port means for injecting control pulses into said medium, each control pulse travels through said medium in the direction of said interacting signal, with the timing of a control pulse, in relation to said interacting signal, controlled to traverse the control by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means for coupling encoded optical data pulses received during a first frame interval, into said control port means; means for encoding each clock pulse, by combining said interacting signal with said associated reference signal after said signals have traveled through said medium, a first frame interval of clock pulses being encoded to be a replica of said first frame of received encoded data pulses; means for coupling said first frame of encoded clock pulses into said control port means, said first frame of encoded clock pulses being used by said encoding means to encode a second frame of clock pulses; and means for outputting said encoded clock pulses.
Claim 28
Dependent Claim 222 words
An optical circuit arrangement comprising an optical transmission medium including controllable propagation speed material; input port means for injecting optical clock pulses into said medium to develop, for each clock pulse, an interacting signal that travels in said medium in one direction and an associated reference signal that travels in said medium in the opposite direction; control port means for injecting control pulses into said medium, each control pulse travels through said medium in the direction of said interacting signal, with the timing of a control pulse, in relation to said interacting signal, controlled to traverse the control by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means for coupling encoded optical data pulses received during a first frame interval, into said control port means; means for encoding each clock pulse, by combining said interacting signal with said associated reference signal after said signals have traveled through said medium, a first frame interval of clock pulses being encoded to be a replica of said first frame of received encoded data pulses; means for coupling said first frame of encoded clock pulses into said control port means, said first frame of encoded clock pulses being used by said encoding means to encode a second frame of clock pulses; and means for outputting said encoded clock pulses.
Claim 29
Dependent Claim 232 words
An optical circuit arrangement comprising an optical transmission medium including controllable propagation speed material; input port means for injecting optical clock pulses into said medium to develop, for each clock pulse, an interacting signal that travels in said medium in one direction and an associated reference signal that travels in said medium in the opposite direction; control port means for injecting control pulses into said medium, each control pulse travels through said medium in the direction of said interacting signal medium in the direction of said interacting signal, with the timing of a control pulse, in relation to said interacting signal, controlled to traverse the control pulse by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means for coupling encoded optical data pulses, received during a first frame interval, into said control port means; means for encoding each clock pulse, by combining said interacting signal with said associated reference signal after said signals have traveled through said medium, a first frame interval of clock pulses being encoded to be an inverse replica of said first frame of received encoded data pulses; means for coupling said first frame of encoded clock pulses into said control port means, said first frame of encoded clock pulse being used by said encoding means to encode a second frame of clock pulses; and means for outputting said encoded clock pulses.
Claim 30
Dependent Claim 232 words
An optical circuit arrangement comprising an optical transmission medium including controllable propagation speed material; input port means for injecting optical clock pulses into said medium to develop, for each clock pulse, an interacting signal that travels in said medium in one direction and an associated reference signal that travels in said medium in the opposite direction; control port means for injecting control pulses into said medium, each control pulse travels through said medium in the direction of said interacting signal medium in the direction of said interacting signal, with the timing of a control pulse, in relation to said interacting signal, controlled to traverse the control pulse by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means for coupling encoded optical data pulses, received during a first frame interval, into said control port means; means for encoding each clock pulse, by combining said interacting signal with said associated reference signal after said signals have traveled through said medium, a first frame interval of clock pulses being encoded to be an inverse replica of said first frame of received encoded data pulses; means for coupling said first frame of encoded clock pulses into said control port means, said first frame of encoded clock pulse being used by said encoding means to encode a second frame of clock pulses; and means for outputting said encoded clock pulses.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-10-13 1996-04-13 1996-10-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-10-13 2000-04-13 2000-10-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-10-13 2004-04-13 2004-10-13 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag