US5155564A
Expired / Lapsed
US
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Thin-film transistor array
Assignee: Sharp Corp
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Filing: 1990-11-21
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Granted: 1992-10-13
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Expires: 2010-11-21
Abstract
Abstract A thin-film transistor array has an insulating substrate; a plurality of thin-film transistors disposed in a matrix form on the substrate; a plurality of gate bus lines formed parallel to each other on the substrate, each of the gate bus lines being connected electrically with the gate electrodes of the thin-film transistors in the corresponding row of the matrix; and a plurality of source bus lines formed perpendicular to the gate bus lines on the substrate, each of the source bus lines being connected electrically with the source electrodes of the thin-film transistors in the corresponding column of the matrix; wherein at the intersections of the gate bus lines and the source bus lines, there is disposed a layered structure between the gate bus line and the source bus line, having successively a gate insulating film, a first semiconductor film, a protective insulating film, and a second semiconductor film which is connected electrically with the source intersections, wherein the width of the protective insulating film in the direction in which the gate bus line extends is equal to or greater than that of the second semiconductor film in that direction.
Inventors
- 👤 Tadanori Hishida
- 👤 Hajime Shoji
- 👤 Hiroshi Hamada
- 👤 Hisato Nagatomi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:57
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/40; H10D86/441; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; G02F1/136286; G02F2202/00; G02F2202/10; G02F2202/103
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
211 words
In a thin-film transistor array comprising: an insulating substrate; a plurality of thin-film transistors disposed in a matrix form on said substrate; a plurality of gate bus lines formed parallel to each other on said substrate, each of said gate bus lines being connected electrically with the gate electrodes of the thin-film transistors in the corresponding row of said matrix; and a plurality of source bus lines formed perpendicular to said gate bus lines on said substrate, each of said source bus lines being connected electrically with the source electrodes of the thin-film transistors in the corresponding column of said matrix; wherein at the intersections of said gate bus lines and said source bus lines, there is disposed a layered structure between the gate bus line and the source bus line, comprising successively a gate insulating film a first semiconductor film made of amorphous silicon, a protective insulating film, and a second semiconductor film connected electrically with said source bus line; the improvement comprising that at said intersections, the width of said protective insulating film in the direction in which said gate bus line extends is equal to or greater than that of said second semiconductor film in said direction and said first semiconductor film is separated from the thin-film transistor.
Claim 2
Dependent Claim
211 words
In a thin-film transistor array comprising: an insulating substrate; a plurality of thin-film transistors disposed in a matrix form on said substrate; a plurality of gate bus lines formed parallel to each other on said substrate, each of said gate bus lines being connected electrically with the gate electrodes of the thin-film transistors in the corresponding row of said matrix; and a plurality of source bus lines formed perpendicular to said gate bus lines on said substrate, each of said source bus lines being connected electrically with the source electrodes of the thin-film transistors in the corresponding column of said matrix; wherein at the intersections of said gate bus lines and said source bus lines, there is disposed a layered structure between the gate bus line and the source bus line, comprising successively a gate insulating film a first semiconductor film made of amorphous silicon, a protective insulating film, and a second semiconductor film connected electrically with said source bus line; the improvement comprising that at said intersections, the width of said protective insulating film in the direction in which said gate bus line extends is equal to or greater than that of said second semiconductor film in said direction and said first semiconductor film is separated from the thin-film transistor.
Claim 3
Dependent Claim
17 words
A thin-film transistor array according to claim 1, wherein said insulating substrate is made of a glass.
Claim 4
Dependent Claim
29 words
A thin-film transistor array according to claim 1, wherein an insulating film made of tantalum oxide is formed on the surface of said gate bus lines by anodic oxidation.
Claim 5
Dependent Claim
83 words
A thin-film transistor array according to claim 1, wherein said gate insulating film comprises an SiN x gate insulating film with a thickness of 1000 to 3000Å, said first semiconductor film comprises an amorphous silicon film with a thickness of 100 to 200 Å, said protective insulating film comprises an SiN x protective insulating film with a thickness of 1000 to 4000Å, and said second semiconductor film comprises a phosphorus-doped n + -type amorphous silicon film with a thickness of 100 to 1000Å.
Claim 6
Dependent Claim
33 words
A thin-film transistor array according to claim 1, wherein said gate insulating film, said first semiconductor film, said protective insulating film, and said second semiconductor film are formed by plasma chemical vapor deposition.
Claim 7
Dependent Claim
26 words
A thin-film transistor array according to claim 1, wherein said gate bus lines are made of tantalum and said source bus lines are made of titanium.
Claim 8
Dependent Claim
243 words
A thin-film transistor array comprising: an insulating substrate made of glass; a plurality of thin-film transistors disposed in a matrix form on said substrate; a plurality of gate bus lines made of tantalum, said gate bus lines being formed parallel to each other on said substrate and connected electrically with the gate electrodes of the thin-film transistors in the corresponding row of said matrix; a plurality of source bus lines consisting of titanium, formed perpendicular to said gate bus lines on said substrate and connected electrically with the source electrodes of the thin-film transistors in the corresponding column of said matrix; and a layered structure disposed between the gate bus line and the source bus line at the intersections thereof, comprising successively at gate insulating film made of SiN x with a thickness of 1000 to 3000Å, a first semiconductor film made of amorphous silicon with a thickness of 100 to 200Å, a protective insulating film made of SiN x with a thickness of 1000 to 4000Å, and a second semiconductor film made of phosphorous-doped n + -type amorphous silicon with a thickness of 100 to 1000Å, said second semiconductor film being connected electrically with said source bus line, wherein the width of said protective insulating film in the direction in which said gate bus line extends is equal to or greater than that of said second semiconductor film in said direction and said first semiconductor film is separated from the thin-film transistor.
Claim 9
Dependent Claim
243 words
A thin-film transistor array comprising: an insulating substrate made of glass; a plurality of thin-film transistors disposed in a matrix form on said substrate; a plurality of gate bus lines made of tantalum, said gate bus lines being formed parallel to each other on said substrate and connected electrically with the gate electrodes of the thin-film transistors in the corresponding row of said matrix; a plurality of source bus lines consisting of titanium, formed perpendicular to said gate bus lines on said substrate and connected electrically with the source electrodes of the thin-film transistors in the corresponding column of said matrix; and a layered structure disposed between the gate bus line and the source bus line at the intersections thereof, comprising successively at gate insulating film made of SiN x with a thickness of 1000 to 3000Å, a first semiconductor film made of amorphous silicon with a thickness of 100 to 200Å, a protective insulating film made of SiN x with a thickness of 1000 to 4000Å, and a second semiconductor film made of phosphorous-doped n + -type amorphous silicon with a thickness of 100 to 1000Å, said second semiconductor film being connected electrically with said source bus line, wherein the width of said protective insulating film in the direction in which said gate bus line extends is equal to or greater than that of said second semiconductor film in said direction and said first semiconductor film is separated from the thin-film transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |