US5153884A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Intelligent network interface circuit
Assignee: Allen Bradley Co LLC
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Filing: 1990-08-15
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Granted: 1992-10-06
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Expires: 2010-08-15
Abstract
Abstract An interface circuit couples a host processor in an industrial control system to a local area communications network. In includes a protocol machine for receiving and transmitting messages on the network and an interface controller which is programmed to implement one or more protocols. As a message is received by the protocol machine, the interface controller anticipates a responsive message which it writes to the protocol machine even as the message is being received. If the message is received accurately, the responsive message is transmitted without delay.
Inventors
- 👤 Mark A. Lucak
- 👤 Jonathon R. Engdahl
- 👤 Michael T. Klein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:53
CPC Classifications
H; H04; H04L; H04L9/00; H04L9/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
218 words
An interface circuit for connection to he communications media of a communications network, the combination comprising: a protocol machine having a receive section which connects to the communications media to receive messages and having a transmit section which connects to the communications media to send messages which are written to the transmit section; and an interface controller connected to the protocol machine and including: (a) means coupled to said receive section for analyzing a control code in a first message as it is received by the receive section of the protocol machine; (b) means coupled to said last named means (a) for writing a responsive second message to the transmit section of the protocol machine while the protocol machine continues to receive the first message; (c) means coupled to said receive section for checking the integrity o the first message when it has been completely received to determine if any errors occurred; (d) means coupled to said last named means (c) for processing the received first message f no errors are detected; and (e) means coupled to said checking means (c) or conducting an error recovery sequence if an error is detected; wherein the transmit section of the protocol machine operates to transmit the second message a preset time interval after the correct receipt of the fit message.
Claim 2
Dependent Claim
218 words
An interface circuit for connection to he communications media of a communications network, the combination comprising: a protocol machine having a receive section which connects to the communications media to receive messages and having a transmit section which connects to the communications media to send messages which are written to the transmit section; and an interface controller connected to the protocol machine and including: (a) means coupled to said receive section for analyzing a control code in a first message as it is received by the receive section of the protocol machine; (b) means coupled to said last named means (a) for writing a responsive second message to the transmit section of the protocol machine while the protocol machine continues to receive the first message; (c) means coupled to said receive section for checking the integrity o the first message when it has been completely received to determine if any errors occurred; (d) means coupled to said last named means (c) for processing the received first message f no errors are detected; and (e) means coupled to said checking means (c) or conducting an error recovery sequence if an error is detected; wherein the transmit section of the protocol machine operates to transmit the second message a preset time interval after the correct receipt of the fit message.
Claim 3
Dependent Claim
17 words
The interface circuit as recited in claim 1 in which the interface controller is a programmed microcomputer.
Claim 4
Dependent Claim
46 words
The interface circuit as recited in claim 2 in which said means for conducting an error recovery sequence includes means for forming a third message and means for writing said third message to the transmit section of the protocol machine in place of said second message.
Claim 5
Dependent Claim
65 words
The interface circuit as recited in claim 1 which further includes a shared memory coupled to the protocol machine for storing messages received by the protocol machine, and the interface controller includes: (f) means coupled to said processing means (d) for signaling a host processor that a received message may be read from the shared memory when no errors are detected in said received message.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |