US5153593A
Expired / Lapsed
US
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Multi-stage sigma-delta analog-to-digital converter
Assignee: Raytheon Co
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Filing: 1990-04-26
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Granted: 1992-10-06
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Expires: 2010-04-26
Abstract
Abstract A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.
Inventors
- 👤 Robert H. Walden
- 👤 Gabor C. Temes
- 👤 Tanju Cataltepe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:15
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/352; H03M3/354; H03M3/39; H03M3/412; H03M3/414; H03M3/416
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
198 words
An analog-to-digital converter for converting an analog input signal of the form X(z) to an output sequence of digital words comprising: a first sigma-delta converter stage including a first multi-bit quantizer for generating a first sequence of digital words and a first quantization error signal e 1 in response to said analog input signal; means for amplifying said error signal by a gain factor G; a second sigma-delta converter stage for generating a second sequence of digital words in response to said amplified quantization error signal; a first noise cancellation network disposed at the output of said first stage including first means for providing a first transfer function H A (z); a second noise cancellation network disposed at the output of said second stage including second means for providing a second transfer function H B (z), said first and second transfer functions being such that said first and second noise cancellation networks are effective, on a summation of the outputs thereof, to substantially eliminate any contribution of the said error signal from the output of said converter; and means for summing the outputs of said first and second noise cancellation networks to provide the output of said converter.
Claim 2
Dependent Claim
198 words
An analog-to-digital converter for converting an analog input signal of the form X(z) to an output sequence of digital words comprising: a first sigma-delta converter stage including a first multi-bit quantizer for generating a first sequence of digital words and a first quantization error signal e 1 in response to said analog input signal; means for amplifying said error signal by a gain factor G; a second sigma-delta converter stage for generating a second sequence of digital words in response to said amplified quantization error signal; a first noise cancellation network disposed at the output of said first stage including first means for providing a first transfer function H A (z); a second noise cancellation network disposed at the output of said second stage including second means for providing a second transfer function H B (z), said first and second transfer functions being such that said first and second noise cancellation networks are effective, on a summation of the outputs thereof, to substantially eliminate any contribution of the said error signal from the output of said converter; and means for summing the outputs of said first and second noise cancellation networks to provide the output of said converter.
Claim 3
Dependent Claim
23 words
The invention of claim 1 including means for amplifying the output of said second noise cancellation stage by a gain factor of 1/G.
Claim 4
Dependent Claim
46 words
The invention of claim 2 wherein said second sigma-delta converter stage includes a second multi-bit quantizer for generating said second sequence of digital words in response to said first quantization error signal, said second multi-bit quantizer having a second quantizer error signal e 2 associated therewith.
Claim 5
Dependent Claim
70 words
The invention of claim 3 wherein said first transfer function H A (z) of said first noise cancellation stage is equal to z -1 , said second transfer function H B (z) of said second noise cancellation stage is equal to (1-z -1 ) and the output voltage of said summing means v out is given by v out =z -2 X(z)-(1/G)z -1 (1-z -1 ) 2 e 2 .
Claim 6
Dependent Claim
91 words
The invention of claim 3 wherein said first sigma-delta converter stage includes a first integrator having a first integration constant k A , said second sigma-delta converter stage includes a second integrator having a second integration constant k B , said first transfer function H A (z) of said first noise cancellation stage is equal to z -1 and said second transfer function H B (z) of said second noise cancellation stage is equal to (z -1 -1)(c+dz -1 ), where c=1/k A k B and d=(1-1/k B )/k A .
Claim 7
Dependent Claim
23 words
The invention of claim 3 wherein said first and said second sigma-delta converter stages include first and second digital to analog converters respectively.
Claim 8
Dependent Claim
34 words
The invention of claim 6 including correction means for modifying said first and second sequences of digital words to correct for nonlinearities in the outputs of said first and second digital to analog converters.
Claim 9
Dependent Claim
13 words
The invention of claim 7 wherein said correction means includes a lookup memory.
Claim 10
Dependent Claim
48 words
The invention of claim 7 wherein said first sigma-delta converter stage includes first integrator having a first operational amplifier having a nonlinearity in the output thereof and said second sigma-delta converter stage includes a second integrator having a second operational amplifier having a nonlinearity in the output thereof.
Claim 11
Dependent Claim
22 words
The invention of claim 9 wherein said correction means includes a digital filter for correcting for said nonlinearities in said operational amplifiers.
References Cited (Backward Citations)
US4862169A
Cited
US4999627A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |