US5153532A
Expired / Lapsed
US
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Noise generator using combined outputs of two pseudo-random sequence generators
Assignee: Honeywell Inc
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Filing: 1989-05-24
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Granted: 1992-10-06
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Expires: 2009-05-24
Abstract
Abstract The pseudo-random-bit sequence generators are clocked by separate clock signals of different frequency. The two pseudo-random-bit sequence generator outputs are logically combined by an exclusive-or gate to provide a pseudo-random-bit sequence generator which, when converted to analog signal has improved white noise characteristics.
Inventors
- 👤 Steven C. Albers
- 👤 Timothy J. Callaghan
- 👤 William L. Rasmussen
- 👤 Robert A. Pajak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:37
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
185 words
A pseudo-random-bit-sequence generator comprising: means for generating a first signal of a first frequency; means for generating a second signal of a second frequency different than said first frequency; a first signal generator, responsive to said first signal, for providing a first pseudo random output signal having a first pseudo-random-bit-sequence having a first selected repeat sequence length which repeats after a selected number of cycles of said first frequency; and a second signal generator, responsive to said second signal, for providing a second pseudo random output signal having a second pseudo-random-bit-sequence having a second repeat sequence length which repeats after a selected number of cycles of said second frequency; and logic means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said logic means operative for logically operating on said first and second pseudo random output signals and providing a third pseudo random output signal having a pseudo-random-bit sequence which is a function of said first and second clock signal frequencies, and said first and second pseudo-random-bit sequences.
Claim 2
Dependent Claim
185 words
A pseudo-random-bit-sequence generator comprising: means for generating a first signal of a first frequency; means for generating a second signal of a second frequency different than said first frequency; a first signal generator, responsive to said first signal, for providing a first pseudo random output signal having a first pseudo-random-bit-sequence having a first selected repeat sequence length which repeats after a selected number of cycles of said first frequency; and a second signal generator, responsive to said second signal, for providing a second pseudo random output signal having a second pseudo-random-bit-sequence having a second repeat sequence length which repeats after a selected number of cycles of said second frequency; and logic means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said logic means operative for logically operating on said first and second pseudo random output signals and providing a third pseudo random output signal having a pseudo-random-bit sequence which is a function of said first and second clock signal frequencies, and said first and second pseudo-random-bit sequences.
Claim 3
Dependent Claim
19 words
The pseudo-random-bit sequence generator of claim 1 wherein said first and second frequencies are non-integer factors of each other.
Claim 4
Dependent Claim
17 words
The pseudo-random-bit sequence generator of claim 1 wherein said first and second repeat sequence lengths are different.
Claim 5
Dependent Claim
32 words
The pseudo-random-bit sequence generator of claim 1 wherein said logic means performs the exclusive-or function, and said third signal is the exclusive-or function of said first and second pseudo random output signals.
Claim 6
Dependent Claim
15 words
The pseudo-random-bit sequence generator of claim 1 wherein said logic means is an EXCLUSIVE-OR gate.
Claim 7
Dependent Claim
206 words
A pseudo-random-bit sequence generator comprising: a signal source for providing a first signal of a first frequency; and first means for operating on said first signal and deriving, therefrom, a second signal of a second frequency and a third signal of a third frequency different than said second frequency; a first signal generator, responsive to said second signal, for providing a first pseudo random output signal having a first pseudo-random-bit sequence having a first selected repeat sequence length which repeats after a selected number of cycles of said second frequency; and a second signal generator, responsive to said third signal, for providing a second pseudo random output signal having a second pseudo-random-bit sequence having a second repeat sequence length which repeats after a selected number of cycles of said third frequency; and logic means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said logic means operative for logically operating on said first and second pseudo random output signals and providing a third pseudo random output signal having a pseudo-random-bit sequence which is a function of said second and third signal frequencies, and said first and second pseudo-random-bit sequences.
Claim 8
Dependent Claim
206 words
A pseudo-random-bit sequence generator comprising: a signal source for providing a first signal of a first frequency; and first means for operating on said first signal and deriving, therefrom, a second signal of a second frequency and a third signal of a third frequency different than said second frequency; a first signal generator, responsive to said second signal, for providing a first pseudo random output signal having a first pseudo-random-bit sequence having a first selected repeat sequence length which repeats after a selected number of cycles of said second frequency; and a second signal generator, responsive to said third signal, for providing a second pseudo random output signal having a second pseudo-random-bit sequence having a second repeat sequence length which repeats after a selected number of cycles of said third frequency; and logic means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said logic means operative for logically operating on said first and second pseudo random output signals and providing a third pseudo random output signal having a pseudo-random-bit sequence which is a function of said second and third signal frequencies, and said first and second pseudo-random-bit sequences.
Claim 9
Dependent Claim
20 words
The pseudo-random-bit sequence generator of claim 6 wherein the said second and third frequencies are non-integer factors of each other.
Claim 10
Dependent Claim
17 words
The pseudo-random-bit sequence generator of claim 6 wherein said first and second repeat sequence lengths are different.
Claim 11
Dependent Claim
32 words
The pseudo-random-bit sequence generator of claim 6 wherein said logic means performs the exclusive-or function, and said third signal is the exclusive-or function of said first and second pseudo random output signals.
Claim 12
Dependent Claim
15 words
The pseudo-random-bit sequence generator of claim 6 wherein said logic means is an EXCLUSIVE-OR gate.
Claim 13
Dependent Claim
132 words
A pseudo-random-bit sequence generator comprising: means for generating a first signal of a first frequency; means for generating a second signal of a second frequency different than said first frequency; a first signal generator, responsive to said first signal, for providing a first pseudo random output signal; and a second signal generator, responsive to said second signal, for providing a second pseudo random output signal; and signal processing means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said signal processing means operative for operating on said first and second pseudo random output signals and providing a third pseudo random output signal representative of the product of said first and second pseudo random output signals.
Claim 14
Dependent Claim
132 words
A pseudo-random-bit sequence generator comprising: means for generating a first signal of a first frequency; means for generating a second signal of a second frequency different than said first frequency; a first signal generator, responsive to said first signal, for providing a first pseudo random output signal; and a second signal generator, responsive to said second signal, for providing a second pseudo random output signal; and signal processing means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said signal processing means operative for operating on said first and second pseudo random output signals and providing a third pseudo random output signal representative of the product of said first and second pseudo random output signals.
Claim 15
Dependent Claim
17 words
The pseudo-random-bit sequence generator of claim 11 wherein said signal processing means serves as a frequency mixer.
Claim 16
Dependent Claim
20 words
The pseudo-random-bit sequence generator of claim 11 wherein the said first and second frequencies are non-integer factors of each other.
Claim 17
Dependent Claim
196 words
A pseudo-random-bit generator comprising: means for generating a first signal of a first frequency; means for generating a second signal of a second frequency different than said first frequency; a first signal generator, responsive to said first signal, for providing a first pseudo random output signal having a first pseudo-random-bit-sequence having a first selected repeat sequence length which repeats after a selected number of cycles of said first frequency; and a second signal generator, responsive to said second signal, for providing a second pseudo random output signal having a second pseudo-random-bit-sequence having a second repeat sequence length different than said first repeat sequence length and said second repeat sequence repeats after a selected number of cycles of said second frequency; and logic means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said logic means operative for logically operating on said first and second pseudo random output signals and providing a third pseudo random output signal having a pseudo-random-bit sequence which is a function of said first and second clock signal frequencies, and said first and second pseudo-random-bit sequences.
Claim 18
Dependent Claim
196 words
A pseudo-random-bit generator comprising: means for generating a first signal of a first frequency; means for generating a second signal of a second frequency different than said first frequency; a first signal generator, responsive to said first signal, for providing a first pseudo random output signal having a first pseudo-random-bit-sequence having a first selected repeat sequence length which repeats after a selected number of cycles of said first frequency; and a second signal generator, responsive to said second signal, for providing a second pseudo random output signal having a second pseudo-random-bit-sequence having a second repeat sequence length different than said first repeat sequence length and said second repeat sequence repeats after a selected number of cycles of said second frequency; and logic means, having an output, a first input for receiving said first pseudo random output signal, and a second input for receiving said second pseudo random output signal, said logic means operative for logically operating on said first and second pseudo random output signals and providing a third pseudo random output signal having a pseudo-random-bit sequence which is a function of said first and second clock signal frequencies, and said first and second pseudo-random-bit sequences.
References Cited (Backward Citations)
US4341925A
Cited
US4653920A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |