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US5153451A
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Fail safe level shifter
Assignee: NXP USA Inc
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Filing: 1991-08-19
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Granted: 1992-10-06
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Expires: 2011-08-19
Abstract
Abstract A fail safe level shifter assures that, when an input signal voltage level falls below a given threshold voltage, the output is either a constant high or no signal at all. Additionally, a range of digital high signals having a voltage less than the given threshold voltage may be shifted by the fail safe level shifter. The fail safe level shifter expands the width of an N-MOS channel of conventional level shifters by placing two MOS switches in parallel. The resultant resistance allows the fail safe level shifter to register those high signals which are below the given threshold voltage. One-half of the level shifter has a N-MOS channel about one-half the width of a N-MOS channel in the other half of the level shifter. Therefore, the narrower half is unable to fully activate given the low input signals received. The fail safe level shifter thus assures that the output will be a constant high.
Inventors
- 👤 Norihisa Yamamura
- 👤 Kazunori Hibino
- 👤 Tatsuo Hayakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:45
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356104; H03K3/356113
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
339 words
A fail safe level shifter, comprising: a first PMOS transistor having first and second current carrying electrodes and a control electrode, said second current carrying electrode of said first PMOS transistor being coupled to a first supply voltage terminal, said control electrode of said first transistor being coupled to provide an output of the fail safe level shifter; a second transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode being coupled to the output of the fail safe level shifter, said second current carrying electrode of said second transistor being coupled to said first supply voltage terminal, said control electrode of said second transistor being coupled to said first current carrying electrode of said first transistor; a third transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said third transistor being coupled to said first current carrying electrode of said second transistor, said second current carrying electrode of said third transistor being coupled to a second supply voltage terminal, and said control electrode of said third transistor being coupled to receive an input signal; a fourth transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said fourth transistor being coupled to said first current carrying electrode of said first transistor, said second current carrying electrode of said fourth transistor being coupled to said second supply voltage terminal, said control electrode of said fourth transistor being coupled to receive the inversion of said input signal; and a fifth transistor having first and second current carrying electrodes and a control electrode, said first and second current carrying electrodes and said control electrode of said fifth transistor being respectively coupled to said first and second current carrying electrodes and said control electrode of said fourth transistor such that said fifth transistor is coupled in parallel with said fourth transistor to increase the width of said fourth transistor thereby decreasing the logical threshold of said second transistor.
Claim 2
Dependent Claim
339 words
A fail safe level shifter, comprising: a first PMOS transistor having first and second current carrying electrodes and a control electrode, said second current carrying electrode of said first PMOS transistor being coupled to a first supply voltage terminal, said control electrode of said first transistor being coupled to provide an output of the fail safe level shifter; a second transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode being coupled to the output of the fail safe level shifter, said second current carrying electrode of said second transistor being coupled to said first supply voltage terminal, said control electrode of said second transistor being coupled to said first current carrying electrode of said first transistor; a third transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said third transistor being coupled to said first current carrying electrode of said second transistor, said second current carrying electrode of said third transistor being coupled to a second supply voltage terminal, and said control electrode of said third transistor being coupled to receive an input signal; a fourth transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said fourth transistor being coupled to said first current carrying electrode of said first transistor, said second current carrying electrode of said fourth transistor being coupled to said second supply voltage terminal, said control electrode of said fourth transistor being coupled to receive the inversion of said input signal; and a fifth transistor having first and second current carrying electrodes and a control electrode, said first and second current carrying electrodes and said control electrode of said fifth transistor being respectively coupled to said first and second current carrying electrodes and said control electrode of said fourth transistor such that said fifth transistor is coupled in parallel with said fourth transistor to increase the width of said fourth transistor thereby decreasing the logical threshold of said second transistor.
Claim 3
Dependent Claim
19 words
The fall safe level shifter according to claim 1, wherein said first and second transistors are PMOS channel transistors.
Claim 4
Dependent Claim
20 words
The fail safe level shifter according to claim 1 wherein said third, fourth and fifth transistors are NMOS channel transistors.
References Cited (Backward Citations)
US4695744A
Cited
US4996443A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |