Keyboard interface system allowing a synchronous keyboard to communicate with a host processor asynchronously by manipulating the keyboard clock's state

Claim 2

In a computer system having a synchronous keyboard, the keyboard having clock signal generation means; a host processor; and interface means connected between the keyboard and the host processor, the interface means having means for receiving serial data from the keyboard, means for providing serial data to the keyboard, means for receiving parallel data from the host processor, means for providing parallel data to the host processor, means connected to the serial data receiving means and the parallel date providing means for converting serial data from the keyboard to parallel form and means connected to the parallel data receiving means and the serial data providing means for converting parallel data from the host processor to serial form, a method for handling data transmissions from said keyboard comprising the steps of a) generating a keyboard clock signal, b) providing the keyboard clock signal to the interface means, c) clocking a scan code from said keyboard into said interface means in synchronization with said keyboard clock signal, d) when the entire scan code has been received by the interface means, inhibiting the keyboard clock signal, e) transmitting the received scan code in parallel from the interface means to the host processor, f) interpreting the received scan code to determine if a transmission from the host processor back to the keyboard in response to the scan code is required, g) if a transmission from the host processor back to the keyboard is not required, releasing the keyboard clock signal, and h) if a transmission from the host processor back to the keyboard is required, performing the transmission from the host processor back to the keyboard.

Claim 3

In a computer system having a synchronous keyboard, the keyboard having first clock signal generation means; a host processor; and interface means connected between the keyboard and the host processor, the interface means having means for receiving serial data from the keyboard, means for providing serial data to the keyboard, means for receiving parallel data from the host processor, means for providing parallel data to the host processor, means connected to the means for receiving serial data and the means for providing parallel data for converting serial data from the keyboard to parallel form, means connected to the means for receiving parallel data and the means for providing serial data for converting parallel data from the host processor to serial form, and second clock signal generation means, a method for handling data transmissions from the host processor to said keyboard comprising the steps of: a) inhibiting receipt of data by the serial data receiving means and inhibiting transmission of data by the serial data providing means, b) loading data to be transmitted to the keyboard from the host processor into the parallel data receiving means, c) enabling the serial data transmitting means, d) supplying the second clock signal to the serial data providing means to initiate data transmission to the keyboard, e) supplying the first clock signal to the serial data providing means to enable clocking of the transmission to the keyboard, f) monitoring for completion of data transmission, and g) when data transmission is complete, disabling the serial data transmission means and enabling the serial data receiving means.

Claim 4

In a computer system having a synchronous keyboard, the keyboard having first clock signal generation means; a host processor; and interface means connected between the keyboard and the host processor, the interface means having means for receiving serial data from the keyboard, means for providing serial data to the keyboard, means for receiving parallel data from the host processor, means for providing parallel data to the host processor, means connected to the means for receiving serial data and the means for providing parallel data for converting serial data from the keyboard to parallel form, means connected to the means for receiving parallel data and the means for providing serial data for converting parallel data from the host processor to serial form, and second clock signal generation means, a method for handling data transmissions from the host processor to said keyboard comprising the steps of: a) inhibiting receipt of data by the serial data receiving means and inhibiting transmission of data by the serial data providing means, b) loading data to be transmitted to the keyboard from the host processor into the parallel data receiving means, c) enabling the serial data transmitting means, d) supplying the second clock signal to the serial data providing means to initiate data transmission to the keyboard, e) supplying the first clock signal to the serial data providing means to enable clocking of the transmission to the keyboard, f) monitoring for completion of data transmission, and g) when data transmission is complete, disabling the serial data transmission means and enabling the serial data receiving means.

Claim 5

Apparatus for controlling parallel-to-serial and serial-to-parallel data transfer between a host processor and a synchronous keyboard, said keyboard having keyboard clock signal generation means, said apparatus comprising: asynchronous data receiving means connected to said host processor and said keyboard, said asynchronous data receiving means including means for receiving data in parallel from said host processor; means for receiving a data receiving clock signal; and means for receiving data serially from said keyboard in synchronization with said data receiving clock signal, asynchronous data transmitting means connected to said host and said keyboard, said asynchronous data transmitting means including means for transmitting data in parallel to said host; means for receiving a data transmitting clock signal; and means for transmitting data serially to said keyboard in synchronization with said data transmitting clock signal; and clock signal control means connected to said keyboard, said asynchronous data receiving means, said asynchronous data transmitting means and said host processor, said clock signal control means including means for receiving the keyboard clock signal generated by the keyboard clock signal generation means; means, responsive to commands from said host processor, for supplying said keyboard clock signal to said asynchronous data receiving means as the data receiving clock signal; means, responsive to commands from said host processor, for supplying said keyboard clock signal to said transmitting means as the data transmitting clock signal, means for generating a second clock signal; and means, responsive to commands from said host processor, for supplying said second clock signal to said transmitting means as the data transmitting clock signal.

Claim 6

Apparatus for controlling parallel-to-serial and serial-to-parallel data transfer between a host processor and a synchronous keyboard, said keyboard having keyboard clock signal generation means, said apparatus comprising: asynchronous data receiving means connected to said host processor and said keyboard, said asynchronous data receiving means including means for receiving data in parallel from said host processor; means for receiving a data receiving clock signal; and means for receiving data serially from said keyboard in synchronization with said data receiving clock signal, asynchronous data transmitting means connected to said host and said keyboard, said asynchronous data transmitting means including means for transmitting data in parallel to said host; means for receiving a data transmitting clock signal; and means for transmitting data serially to said keyboard in synchronization with said data transmitting clock signal; and clock signal control means connected to said keyboard, said asynchronous data receiving means, said asynchronous data transmitting means and said host processor, said clock signal control means including means for receiving the keyboard clock signal generated by the keyboard clock signal generation means; means, responsive to commands from said host processor, for supplying said keyboard clock signal to said asynchronous data receiving means as the data receiving clock signal; means, responsive to commands from said host processor, for supplying said keyboard clock signal to said transmitting means as the data transmitting clock signal, means for generating a second clock signal; and means, responsive to commands from said host processor, for supplying said second clock signal to said transmitting means as the data transmitting clock signal.

Claim 7

The apparatus of claim 3 wherein said clock signal control means further includes means, responsive to commands from the host processor, for inhibiting the generation of the keyboard clock signal.

Claim 8

Apparatus for controlling parallel-to-serial and serial-to-parallel data transfer between a host processor and a synchronous keyboard, said keyboard having keyboard clock signal generation means, said apparatus comprising: asynchronous receiver/transmitter means connected to said host processor and said keyboard, said asynchronous receiver/transmitter including means for receiving data in parallel from said host; means for supplying data serially to said keyboard; means for receiving data serially from said keyboard; means for supplying data in parallel to said host; and means for receiving a data clock signal; and clock signal control means connected to said keyboard, said receiver/transmitter means and said host processor, said clock signal control means including means for receiving the keyboard clock signal generated by the keyboard clock signal generation means; means, responsive to commands from said host processor, for supplying said keyboard clock signal to said receiver/transmitter means as the data clock signal; means for generating a second clock signal; means, responsive to commands from said host processor, for supplying said second clock signal to said receiver/transmitter means as the data clock signal.

Claim 9

Apparatus for controlling parallel-to-serial and serial-to-parallel data transfer between a host processor and a synchronous keyboard, said keyboard having keyboard clock signal generation means, said apparatus comprising: asynchronous receiver/transmitter means connected to said host processor and said keyboard, said asynchronous receiver/transmitter including means for receiving data in parallel from said host; means for supplying data serially to said keyboard; means for receiving data serially from said keyboard; means for supplying data in parallel to said host; and means for receiving a data clock signal; and clock signal control means connected to said keyboard, said receiver/transmitter means and said host processor, said clock signal control means including means for receiving the keyboard clock signal generated by the keyboard clock signal generation means; means, responsive to commands from said host processor, for supplying said keyboard clock signal to said receiver/transmitter means as the data clock signal; means for generating a second clock signal; means, responsive to commands from said host processor, for supplying said second clock signal to said receiver/transmitter means as the data clock signal.

Claim 10

The apparatus of claim 5 wherein said clock signal control means further includes means, responsive to commands from the host processor, for inhibiting the generation of the keyboard clock signal.