Data processor

Claim 2

A data processor having a multifrequency receiver formed together with a central processor on a semiconductor substrate, said multifrequency receiver comprising means for separating a tone wave from an analog signal including multiple frequencies; means for shaping a waveform of the separated tone wave to form a shaped signal; means for forming digital data representative of a type of tone wave on a basis of the shaped signal in accordance with information provided by said central processor; and data holding means for holding formed digital data so that said digital data is accessible by said central processor.

Claim 3

The data processor according to claim 1, wherein said central processor possesses reference data for identifying a tone wave included in the analog signal including multiple frequencies, said multifrequency receiver having a means for identifying the type of tone wave included in a signal fed to said multifrequency receiver on a basis of said reference data and said digital data retrieved from said data holding means.

Claim 4

The data processor according to claim 2 further comprising a flag means for indicating, to said central processor, a load state of said digital data into said data holding means, said central processor having means for sampling a state of said flag and means for accessing said data holding means in response to a set state of said flag.

Claim 5

The data processor according to claim 3, wherein said central processor has means for resetting said flag, said data holding means having gate means in an input stage thereof, said multifrequency receiver comprising means for controlling said gate means so that digital data loaded into said data holding means is held until said flag is reset.

Claim 6

The data processor according to claim 4, wherein said digital data forming means comprises a period counter which counts a clock signal in a preselected relation with an operational reference clock signal of said central processor at an interval defined as a half period of a multiple of a period of a shaped signal.

Claim 7

The data processor according to claim 5, wherein said digital data forming means comprises an edge generation circuit which generates a pulse in every half period or every period of the shaped signal; an edge counter which counts pulses provided by said edge generation circuit repeatedly up to a predetermined value and clears said period counter when the predetermined value is reached, and a mode register which sets said predetermined count value to be counted repeatedly by said edge counter in accordance with access control received from said central processor.

Claim 8

The data processor according to claim 6, wherein the signal produced by said edge counter for clearing said period counter is supplied to said flag as a signal for setting said flag.

Claim 9

A data processor having a multifrequency receiver formed together with a central processor on a semiconductor substrate, said multifrequency receiver comprising means for separating a tone wave from an analog signal including multiple frequencies; means for shaping the waveform of the separated tone wave; means for forming digital data which correlates with a period of the tone wave on the basis of a shaped signal in accordance with information provided by said central processor; means for setting reference data for tone wave discrimination in accordance with access control of said central processor; means for discriminating a type of tone wave by comparison of data in said reference data setting means with said digital data; and memory means for holding data representative of an identified tone wave so that said representative data is accessible by said central processor.

Claim 10

A data processor having a multifrequency receiver formed together with a central processor on a semiconductor substrate, said multifrequency receiver comprising means for separating a tone wave from an analog signal including multiple frequencies; means for shaping the waveform of the separated tone wave; means for forming digital data which correlates with a period of the tone wave on the basis of a shaped signal in accordance with information provided by said central processor; means for setting reference data for tone wave discrimination in accordance with access control of said central processor; means for discriminating a type of tone wave by comparison of data in said reference data setting means with said digital data; and memory means for holding data representative of an identified tone wave so that said representative data is accessible by said central processor.

Claim 13

The method of claim 9 further comprising the step of identifying a type of tone in accordance with the digital data.

Claim 14

The method of claim 10 further comprising the step of generating a flag representative of a completion of the step of storing formed digital data in the memory.

Claim 15

A single-chip microcomputer comprising: an external terminal for receiving an analog signal, the analog signal including, a first frequency signal selected from a plurality of low-band frequency signals, and a second frequency signal, different from the first frequency signal, selected from a plurality of high-band frequency signals; receiver means coupled to the external terminal and coupled to receive the analog signal for providing digital data representative of kinds of the first and second frequency signals, the receiver including means for generating a ready signal indicating that the digital data is provided, the receiver means further including data registers for storing the digital data therein; and a central processing unit coupled to the receiver means and responsive to the ready signal for accessing the data registers to obtain the digital data, the central processing unit further including means for discriminating the kinds of the first and second frequency signals in accordance with the digital data wherein the receiver means includes counter means for providing the digital data in accordance with information provided form the central processing unit, the counter means executing its count operation to provide the digital data in accordance with clock signals in a predetermined relation with operational clock signals of the central processing unit.

Claim 16

A single-chip microcomputer comprising: an external terminal for receiving an analog signal, the analog signal including, a first frequency signal selected from a plurality of low-band frequency signals, and a second frequency signal, different from the first frequency signal, selected from a plurality of high-band frequency signals; receiver means coupled to the external terminal and coupled to receive the analog signal for providing digital data representative of kinds of the first and second frequency signals, the receiver including means for generating a ready signal indicating that the digital data is provided, the receiver means further including data registers for storing the digital data therein; and a central processing unit coupled to the receiver means and responsive to the ready signal for accessing the data registers to obtain the digital data, the central processing unit further including means for discriminating the kinds of the first and second frequency signals in accordance with the digital data wherein the receiver means includes counter means for providing the digital data in accordance with information provided form the central processing unit, the counter means executing its count operation to provide the digital data in accordance with clock signals in a predetermined relation with operational clock signals of the central processing unit.

Claim 17

The single-chip microcomputer of claim 12, wherein the receiver means further includes: a first filter coupled to receive the analog signal for separating the first frequency signal from the analog signal; a second filter coupled to receive the analog signal for separating the second frequency signal from the analog signal; the counter means including a first circuit coupled to the first filter and responsive to the first frequency signal for providing the digital data to one of the data registers, and a second circuit coupled to the second filter and responsive to the second frequency signal for providing the digital data to the other of the data registers; and a control circuit coupled to the central processing unit and to the first and second circuit for controlling operations of the first and second circuits under control of the central processing unit, the control circuit including means for providing the ready signal to the central processing unit.

Claim 18

The single-chip microcomputer of claim 13 wherein the first and second filters include switched capacitor filters.

Claim 19

The single-chip microcomputer of claim 13 wherein the first and second filters include analog filters.

Claim 20

The single-chip microcomputer of claim 12 wherein the receiver means includes filter means operated for the respective high-band and low-band frequency signals.

Claim 21

The single-chip microcomputer of claim 12 wherein the analog signal includes a tone signal.

Claim 22

The single-chip microcomputer of claim 12, wherein the receiver means further includes: a first filter coupled to receive the analog signal for separating the first frequency signal from the analog signal; a second filter coupled to receive the analog signal for separating the second frequency signal from the analog signal; the counter means including a first circuit coupled to the first filter and responsive to the first frequency signal for providing the digital data to one of the data registers, and a second circuit coupled to the first filter and responsive to the second frequency signal for providing the digital data to the other of the data registers; and a control circuit coupled to the central processing unit and to the first and second circuits for controlling operations of the first and second circuits under control of the central processing unit, the control circuit including means for providing the ready signal to the central processing unit.

Claim 23

The signal-chip microcomputer of claim 12 wherein the receiver means includes filter means operated for the respective high-band and low-band frequency signals.