US5144158A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL latch circuit having a noise resistance circuit in only one feedback path
Assignee: Fujitsu Ltd
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Filing: 1990-04-17
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Granted: 1992-09-01
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Expires: 2010-04-17
Abstract
Abstract A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal ( &upbar& C) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.
Inventors
- 👤 Yasunori Kanai
- 👤 Kazumasa Nawata
- 👤 Mitsuhisa Shimizu
- 👤 Hiroki Yada
- 👤 Taichi Saitoh
- 👤 Toshiaki Sakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:09
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/013; H03K3/02; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
214 words
A latch circuit comprising: a first gate circuit having input terminals for receiving a data signal and a clock signal, and having an output terminal providing the data signal in response to the clock signal; a second gate circuit having a first input terminal operatively connected to the output terminal of said first gate circuit for receiving the data signal, having a second input terminal and having an output terminal; a third gate circuit having a first input terminal operatively connected to receive an inverted clock signal, having a second input terminal and having first and second output terminals; a first feedback line connected between the output terminal of said second gate circuit and the second input terminal of said third gate circuit; a second feedback line connected between the first output terminal of said third gate circuit and the second input terminal of said second gate circuit, the second output terminal of said third gate circuit and the output germinal of said second gate circuit outputting complementary signals in response to a latched state of said latch circuit; and noise resistance means, operatively connected to only said second feedback line including at least a signal delay element, for eliminating noise in said second feedback line and maintaining operation speed of said latch circuit.
Claim 2
Dependent Claim
214 words
A latch circuit comprising: a first gate circuit having input terminals for receiving a data signal and a clock signal, and having an output terminal providing the data signal in response to the clock signal; a second gate circuit having a first input terminal operatively connected to the output terminal of said first gate circuit for receiving the data signal, having a second input terminal and having an output terminal; a third gate circuit having a first input terminal operatively connected to receive an inverted clock signal, having a second input terminal and having first and second output terminals; a first feedback line connected between the output terminal of said second gate circuit and the second input terminal of said third gate circuit; a second feedback line connected between the first output terminal of said third gate circuit and the second input terminal of said second gate circuit, the second output terminal of said third gate circuit and the output germinal of said second gate circuit outputting complementary signals in response to a latched state of said latch circuit; and noise resistance means, operatively connected to only said second feedback line including at least a signal delay element, for eliminating noise in said second feedback line and maintaining operation speed of said latch circuit.
Claim 3
Dependent Claim
17 words
A latch circuit according to claim 1, wherein said noise resistance circuit further includes a filter circuit.
Claim 4
Dependent Claim
19 words
A latch circuit according to claim 2, wherein said first, second and third gate circuits are NOR gate circuits.
Claim 5
Dependent Claim
24 words
A latch circuit according to claim 2 wherein said filter circuit includes: a resistor; and a capacitor operatively connected in series with said resistor.
Claim 6
Dependent Claim
17 words
A latch circuit according to claim 4, wherein said latch circuit is formed in a semiconductor device.
Claim 7
Dependent Claim
16 words
A latch circuit according to claim 5, wherein said resistor is formed in a diffused region.
Claim 8
Dependent Claim
22 words
A latch circuit according to claim 6, wherein said capacitor is formed in a depletion layer adjacent to said resistor diffused region.
Claim 9
Dependent Claim
17 words
A latch circuit according to claim 1, wherein said latch circuit is formed in a semiconductor device.
Claim 10
Dependent Claim
16 words
A latch circuit according to claim 8, wherein said semiconductor device is a bipolar-type semiconductor device.
Claim 11
Dependent Claim
16 words
A latch circuit according to claim 9, wherein said gate circuits are formed employing emitter-coupled logic.
Claim 12
Dependent Claim
248 words
A latch circuit, comprising: a first OR gate circuit, operatively connected to receive a data signal and a clock signal, and having a noninverted output terminal and an inverted output terminal; a second OR gate circuit having a first input terminal operatively connected to receive an inverted clock signal and having a second input terminal, a non-inverted output terminal, and an inverted output terminal; an AND gate circuit having first and second input terminals and having first and second output terminals; a wired OR gate circuit having first and second input terminals, said non-inverted output terminal of said first OR gate circuit operatively connected to the first input terminal of said AND gate circuit, and said inverted output terminal of said first OR gate circuit operatively connected to the first input terminal of said wired OR gate circuit, said inverted output terminal of said second OR gate circuit operatively connected to the second input terminal of said wired OR gate circuit, and said non-inverted output terminal of said second OR gate circuit operatively connected to the second input terminal of said AND gate circuit, an output terminal of said wired OR gate circuit and the first output terminal of said AND gate circuit outputting complementary signals; a feedback line connected between the second output terminal of said AND gate circuit and the second input terminal of said second OR gate circuit; and noise resistance means, operatively connected to said feedback line, including at least a signal delay element.
Claim 13
Dependent Claim
248 words
A latch circuit, comprising: a first OR gate circuit, operatively connected to receive a data signal and a clock signal, and having a noninverted output terminal and an inverted output terminal; a second OR gate circuit having a first input terminal operatively connected to receive an inverted clock signal and having a second input terminal, a non-inverted output terminal, and an inverted output terminal; an AND gate circuit having first and second input terminals and having first and second output terminals; a wired OR gate circuit having first and second input terminals, said non-inverted output terminal of said first OR gate circuit operatively connected to the first input terminal of said AND gate circuit, and said inverted output terminal of said first OR gate circuit operatively connected to the first input terminal of said wired OR gate circuit, said inverted output terminal of said second OR gate circuit operatively connected to the second input terminal of said wired OR gate circuit, and said non-inverted output terminal of said second OR gate circuit operatively connected to the second input terminal of said AND gate circuit, an output terminal of said wired OR gate circuit and the first output terminal of said AND gate circuit outputting complementary signals; a feedback line connected between the second output terminal of said AND gate circuit and the second input terminal of said second OR gate circuit; and noise resistance means, operatively connected to said feedback line, including at least a signal delay element.
Claim 14
Dependent Claim
151 words
A latch circuit comprising: a first gate circuit for receiving a data signal and a clock signal, and having an output terminal outputting the data signal in response to the clock signal; a second gate circuit having a first input terminal operatively connected to said output terminal of said first gate circuit and having a second input terminal, and having first and second output terminals; a third gate circuit having first and second input terminals and having first and second output terminal; a first feedback line connected between said second output terminal of said second gate circuit and said second input terminal of said third gate circuit; a second feedback line connected between said first output terminal of said third gate circuit and said second input terminal of said second gate circuit; and noise resistance means, operatively connected to only said first feedback line, including at least a signal delay element.
Claim 15
Dependent Claim
151 words
A latch circuit comprising: a first gate circuit for receiving a data signal and a clock signal, and having an output terminal outputting the data signal in response to the clock signal; a second gate circuit having a first input terminal operatively connected to said output terminal of said first gate circuit and having a second input terminal, and having first and second output terminals; a third gate circuit having first and second input terminals and having first and second output terminal; a first feedback line connected between said second output terminal of said second gate circuit and said second input terminal of said third gate circuit; a second feedback line connected between said first output terminal of said third gate circuit and said second input terminal of said second gate circuit; and noise resistance means, operatively connected to only said first feedback line, including at least a signal delay element.
Claim 16
Dependent Claim
26 words
A latch circuit according to claim 12, wherein one of said first and second output terminals of said third gate circuit is a non-inverted output terminal.
Claim 17
Dependent Claim
241 words
A latch circuit comprising: a first gate circuit having input terminals for receiving a data signal and a clock signal, and having an output terminal providing the data signal in response to the clock signal; a second gate circuit having a first input terminal operatively connected to the output terminal of said first gate circuit for receiving the data signal, having a second input terminal, and having an output terminal; a third gate circuit having a first input terminal operatively connected to receive an inverted clock signal, having a second input terminal, and having first and second output terminals; a first feedback line connected between the output terminal of said second gate circuit and the second input terminal of said third gate circuit; a second feedback line connected between the first output terminal of said third gate circuit and the second input terminal of said second gate circuit, the second output terminal of said third gate circuit and the output terminal of said second gate circuit outputting complementary signals in response to a latched state of said latch circuit; and noise resistance means, operatively connected to only said second feedback line, including at least a signal delay element, for eliminating noise in said second feedback line and maintaining operation speed of said latch circuit, said noise resistance circuit including: an amplifier circuit including a signal delay element having a predetermined delay time and a signal amplifying element having a predetermined amplification.
Claim 18
Dependent Claim
241 words
A latch circuit comprising: a first gate circuit having input terminals for receiving a data signal and a clock signal, and having an output terminal providing the data signal in response to the clock signal; a second gate circuit having a first input terminal operatively connected to the output terminal of said first gate circuit for receiving the data signal, having a second input terminal, and having an output terminal; a third gate circuit having a first input terminal operatively connected to receive an inverted clock signal, having a second input terminal, and having first and second output terminals; a first feedback line connected between the output terminal of said second gate circuit and the second input terminal of said third gate circuit; a second feedback line connected between the first output terminal of said third gate circuit and the second input terminal of said second gate circuit, the second output terminal of said third gate circuit and the output terminal of said second gate circuit outputting complementary signals in response to a latched state of said latch circuit; and noise resistance means, operatively connected to only said second feedback line, including at least a signal delay element, for eliminating noise in said second feedback line and maintaining operation speed of said latch circuit, said noise resistance circuit including: an amplifier circuit including a signal delay element having a predetermined delay time and a signal amplifying element having a predetermined amplification.
Claim 19
Dependent Claim
15 words
A latch circuit according to claim 14, wherein said amplifier circuit includes a differential amplifier.
Claim 20
Dependent Claim
13 words
A latch circuit according to claim 15, wherein said differential amplifier includes transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-01 | 1996-03-02 | 1996-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-01 | 2000-03-02 | 2000-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-01 | 2004-03-02 | 2004-09-01 | $7700.00 | Window Closed / Lapsed |