US5142675A
Expired / Lapsed
US
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Monitor channel system in use with a recording apparatus
Assignee: Fujifilm Business Innovation Corp
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Filing: 1990-03-01
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Granted: 1992-08-25
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Expires: 2010-03-01
Abstract
Abstract A monitor control system comprises an interrupt processor for executing regular monitor processing by a periodic interrupt occurring at a predetermined time interval, and a background processor for executing background processing, wherein when interruption occurs, execution of the background processing by the background processor is interrupted while regular monitor processing is executed during a period in which background processing is interrupted. The time-consuming background processing is treated as a low-level processing task, and the regular monitor processing, as a high-level processing task. The low-level processing task is executed as a background processing during CPU idle time. Interruption of the background processing occurs ever 10-msec, during which the high-level processing task is executed. Accordingly, background processing and regular monitor processing are smoothly executed, and the CPU is thereby efficiently used.
Inventors
- 👤 Koichi Oi
- 👤 Takashi Hoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
109 words
A monitor control system having a processor, said processor comprising: interrupt means for executing a regular monitor process by an interrupt occurring at a predetermined time interval; background processing means for executing a background process; control means for controlling said interrupt means and said background processing means such that said interrupt means executes the regular monitor process during a period in which said background processing means is interrupted; a prestored task table in which prestored tasks to be executed by said background processing means are stored; and a plurality of loop counters for counting a number of processing loops representing a number of executed tasks for each prestored task.
Claim 2
Dependent Claim
109 words
A monitor control system having a processor, said processor comprising: interrupt means for executing a regular monitor process by an interrupt occurring at a predetermined time interval; background processing means for executing a background process; control means for controlling said interrupt means and said background processing means such that said interrupt means executes the regular monitor process during a period in which said background processing means is interrupted; a prestored task table in which prestored tasks to be executed by said background processing means are stored; and a plurality of loop counters for counting a number of processing loops representing a number of executed tasks for each prestored task.
Claim 3
Dependent Claim
20 words
The monitor control system according to claim 1, further comprising a task state table for managing said prestored task table.
Claim 4
Dependent Claim
31 words
The monitor control system according to claim 1, wherein a state indicating completion of the prestored tasks is held for a predetermined time until said background processing means is next interrupted.
Claim 5
Dependent Claim
21 words
The monitor control system according to claim 1, wherein said background process is a calculating process requiring 10 msec or more.
Claim 6
Dependent Claim
35 words
The monitor control system according to claim 1, wherein said prestored tasks to be executed by said background processing means are stored and erased by a supervisor call produced in accordance with said interrupt means.
Claim 7
Dependent Claim
112 words
A monitor control system having a processor, said processor comprising: interrupt means for executing a regular monitor process by an interrupt occurring at a predetermined time interval; background processing means for executing a background process; control means for controlling said interrupt means and said background processing means such that said interrupt means executes the regular monitor process during a period in which said background processing means is interrupted; a prestored task table in which prestored tasks to be executed by said background processing means are stored, wherein upon execution of one of the prestored tasks in said prestored task table, a number representative of the number of said prestored tasks is decremented.
Claim 8
Dependent Claim
112 words
A monitor control system having a processor, said processor comprising: interrupt means for executing a regular monitor process by an interrupt occurring at a predetermined time interval; background processing means for executing a background process; control means for controlling said interrupt means and said background processing means such that said interrupt means executes the regular monitor process during a period in which said background processing means is interrupted; a prestored task table in which prestored tasks to be executed by said background processing means are stored, wherein upon execution of one of the prestored tasks in said prestored task table, a number representative of the number of said prestored tasks is decremented.
Claim 9
Dependent Claim
31 words
The monitor control system according to claim 6, wherein a state indicating completion of the prestored tasks is held for a predetermined time until said background processing means is next interrupted.
Claim 10
Dependent Claim
21 words
The monitor control system according to claim 6, wherein said background process is a calculating process requiring 10 msec or more.
Claim 11
Dependent Claim
35 words
The monitor control system according to claim 6, wherein said prestored tasks to be executed by said background processing means are stored and erased by a supervisor call produced in accordance with said interrupt means.
Claim 12
Dependent Claim
127 words
A monitor control system comprising: a plurality of communication processors having different communication speeds; one of said plurality of communication processors comprising interrupt means for executing a regular monitor process in accordance with an interrupt occurring every 10 msec and for executing other processes in accordance with other interrupts; another of said plurality of communication processors comprising background processing means for constantly executing a background process, said background processing means being motivated upon power-on; wherein said one of said plurality of communication processors has a high processing speed relative to the another processor; and control means for controlling said interrupt means and said background processing means such that said interrupt means executes the regular monitor process during a period in which said background processing means is interrupted.
Claim 13
Dependent Claim
127 words
A monitor control system comprising: a plurality of communication processors having different communication speeds; one of said plurality of communication processors comprising interrupt means for executing a regular monitor process in accordance with an interrupt occurring every 10 msec and for executing other processes in accordance with other interrupts; another of said plurality of communication processors comprising background processing means for constantly executing a background process, said background processing means being motivated upon power-on; wherein said one of said plurality of communication processors has a high processing speed relative to the another processor; and control means for controlling said interrupt means and said background processing means such that said interrupt means executes the regular monitor process during a period in which said background processing means is interrupted.
Claim 14
Dependent Claim
30 words
The monitor control system according to claim 10, wherein upon one of said other interrupts and said 10 msec interrupt concurrently occurring, one of said concurrently occurring interrupts is masked.
Claim 15
Dependent Claim
72 words
The monitor control system according to claim 10, wherein said high speed communication processor performs a plurality of communication processing functions, responsive to said other interrupts, and includes a plurality of transmission buffers and a plurality of reception buffers responsive to said high speed communication processor, such that read and write operations, and transmission and reception of data are concurrently performed between said high speed communication processor and a plurality of sources.
Claim 16
Dependent Claim
25 words
The monitor control system according to claim 12, wherein said high speed communication processor transmits to and receives data packets from said plurality of sources.
Claim 17
Dependent Claim
29 words
The monitor control system according to claim 12, wherein said high speed communication processor assigns said transmission buffers and said reception buffers to a particular one of said sources.
Claim 18
Dependent Claim
30 words
The monitor control system according to claim 10, wherein one of said plurality of communication processors is a polling type communication processor for transmitting and receiving data byte by byte.
Claim 19
Dependent Claim
26 words
The monitor control system according to claim 15, wherein said polling type communication processor is motivated by an interruption generated when data is transmitted and received.
Claim 20
Dependent Claim
56 words
The monitor control system according to claim 15, wherein said polling type communication processor includes a line error monitor processor for determining whether an error has occurred in the monitor process and a line error check processor for sending an error message indicating a line error to an application software operating in a monitor central system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-25 | 1996-02-24 | 1996-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-25 | 2000-02-24 | 2000-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-25 | 2004-02-24 | 2004-08-25 | $7700.00 | Window Closed / Lapsed |