Method and apparatus for changing the position of a digitally generated television special effect boundary

Claim 3

The method of claim 1, wherein only a few of the significant bits of said least significant product are used for said control signal.

Claim 4

The method of claim 1, wherein said control signal is proportional to a value obtained by inverting said least significant product of said digital data,

Claim 5

The method of claim 1, wherein by means of said control signal a line by line progressive phase shift of said clock signal is produced to which each step of phase shift is equal to the same fraction of a clock pulse period of said clock pulses.

Claim 8

Apparatus for shifting the position of a digitally generated special effect boundary pattern for television wipe-mixing, comprising: a clock pulse oscillator (1) connected in a phase locked loop circuit (PLL) for locking the frequency of said oscillator to pulses of a television horizontal frequency supplied at an input of said phase locked loop circuit; gate circuit means, (2), having inputs connected to a clock pulse output of said oscillator and to a television horizontal synchronizing signal, for providing first, second and third output pulses at respective outputs during horizontal blanking intervals and providing clock pulses at a fourth output in continuous sequences except during intervals briefly preceding and following said first, second and third output pulses; a controllably variable digital delay line having an output, a first input connected to said fourth output of said gate circuit means (2) and a second input which is a delay control input; a boundary shift-control counter (3) having an output, a count pulse input (T) connected to the output of said delay line, a data input (D) and a load pulse input (Ld) for timing the loading of said counter with data supplied at said data input, said load pulse input being connected to said first output of said gate circuit means; a ramp signal generator (5) having an output and means including a frequency divider (6) for synchronizing its output with said oscillator; a digital multiplier (7) having a first data input connected to said output of said ramp signal generator (5) and a second data input connected to a source of selectable amplitude data for producing at a first output (9') a less significant product (LSP) including the least significant product (MSP) including the most significant product bit and excluding the bits of said less significant product; an inverter stage (8) having an input connected to a source of a derived from said first (LSP) output (9') of said multiplier (7) and an output connected to said control input of said delay line (4): a digital addition state (11) having one input connected to said second (MSP) output (9) of said digital multiplier (7), a second input connected to a source of externally controllable positioning data and an output connected to said data input (D) of said counter (7); a digital-to-analog converter (14) having an input connected to said output of said counter (3) and having an output, a comparator (15) having an output, a first input connected to said output of said digital-to-analog converter (14) and a second input connected to a source of externally controllable fading control data, said comparator output being a source of a special effect boundary pattern control signal.

Claim 9

Apparatus for shifting the position of a digitally generated special effect boundary pattern for television wipe-mixing, comprising: a clock pulse oscillator (1) connected in a phase locked loop circuit (PLL) for locking the frequency of said oscillator to pulses of a television horizontal frequency supplied at an input of said phase locked loop circuit; gate circuit means, (2), having inputs connected to a clock pulse output of said oscillator and to a television horizontal synchronizing signal, for providing first, second and third output pulses at respective outputs during horizontal blanking intervals and providing clock pulses at a fourth output in continuous sequences except during intervals briefly preceding and following said first, second and third output pulses; a controllably variable digital delay line having an output, a first input connected to said fourth output of said gate circuit means (2) and a second input which is a delay control input; a boundary shift-control counter (3) having an output, a count pulse input (T) connected to the output of said delay line, a data input (D) and a load pulse input (Ld) for timing the loading of said counter with data supplied at said data input, said load pulse input being connected to said first output of said gate circuit means; a ramp signal generator (5) having an output and means including a frequency divider (6) for synchronizing its output with said oscillator; a digital multiplier (7) having a first data input connected to said output of said ramp signal generator (5) and a second data input connected to a source of selectable amplitude data for producing at a first output (9') a less significant product (LSP) including the least significant product (MSP) including the most significant product bit and excluding the bits of said less significant product; an inverter stage (8) having an input connected to a source of a derived from said first (LSP) output (9') of said multiplier (7) and an output connected to said control input of said delay line (4): a digital addition state (11) having one input connected to said second (MSP) output (9) of said digital multiplier (7), a second input connected to a source of externally controllable positioning data and an output connected to said data input (D) of said counter (7); a digital-to-analog converter (14) having an input connected to said output of said counter (3) and having an output, a comparator (15) having an output, a first input connected to said output of said digital-to-analog converter (14) and a second input connected to a source of externally controllable fading control data, said comparator output being a source of a special effect boundary pattern control signal.

Claim 10

The apparatus of claim 6, wherein those output of gate circuit means for said second and third output pulses are connected for respectively loading and unloading said digital multiplier (7).

Claim 11

The apparatus of claim 6, wherein said ramp signal generator includes means for storing various selectable ramp signals and means for selecting one of said selectable ramp signals for supply to said multiplier under control of a computer external to said apparatus.