US5140299A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Article comprising a high value resistor
Assignee: Nokia Bell Labs
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Filing: 1990-06-19
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Granted: 1992-08-18
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Expires: 2010-06-19
Abstract
Abstract In an electronic circuit that normally includes a high-value resistor, the resistive function may be usefully provided by a thin dielectric layer. Electric current is transported through the layer by quantum tunneling. In one embodiment, a resistor useful for VLSI applications is provided, requiring only a single contact window.
Inventors
- 👤 John M. Andrews, Jr.
- 👤 San-Chin Fang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:26
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/165; H01; H01C; H01C7/00; H01C7/006; H10D1/00; H10D1/40; H10D12/00; H10D84/00; H10D84/201; H10D84/204; H10D84/209; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
174 words
A metal oxide semiconductor integrated circuit which comprises a silicon substrate, at least one two-terminal circuit element overlying at least a portion of the substrate, and at least one active device electrically connected to the circuit element, the circuit element having first and second contact regions and offering an electrical resistance greater than about 10 7 ohms when a predetermined voltage greater than about 0.1 V is applied across the contact regions, characterized in that the circuit element comprises a first dielectric layer which is disposed between the contact regions such that essentially all direct electric current flowing between the contact regions is transported through the first dielectric layer by quantum tunneling; the first contact region comprises a first polycrystalline silicon layer underlying and in direct contact with the first dielectric layer; the second contact region comprises a heavily doped second polycrystalline silicon layer overlying and in direct contact with the first dielectric layer; and the active device is electrically connected to the circuit element through at least one of the polycrystalline silicon layers.
Claim 2
Dependent Claim
174 words
A metal oxide semiconductor integrated circuit which comprises a silicon substrate, at least one two-terminal circuit element overlying at least a portion of the substrate, and at least one active device electrically connected to the circuit element, the circuit element having first and second contact regions and offering an electrical resistance greater than about 10 7 ohms when a predetermined voltage greater than about 0.1 V is applied across the contact regions, characterized in that the circuit element comprises a first dielectric layer which is disposed between the contact regions such that essentially all direct electric current flowing between the contact regions is transported through the first dielectric layer by quantum tunneling; the first contact region comprises a first polycrystalline silicon layer underlying and in direct contact with the first dielectric layer; the second contact region comprises a heavily doped second polycrystalline silicon layer overlying and in direct contact with the first dielectric layer; and the active device is electrically connected to the circuit element through at least one of the polycrystalline silicon layers.
Claim 3
Dependent Claim
37 words
The circuit of claim 1, wherein the first dielectric layer comprises silicon dioxide or silicon nitride, and the thickness of the first dielectric layer is at least about 10 Å but not more than about 200 Å.
Claim 4
Dependent Claim
19 words
The article of claim 1, further comprising at least one active device electrically connected to the passive circuit element.
Claim 5
Dependent Claim
41 words
The circuit of claim 1, wherein the active device is a bipolar transistor having an emitter, a collector, and a base, and the passive circuit element is electrically connected to at least one of the emitter, the collector, and the base.
Claim 6
Dependent Claim
37 words
The circuit of claim 1, wherein the active device is a field-effect transistor having a source and a drain, and the passive circuit element is electrically connected to at least one of the source and the drain.
Claim 7
Dependent Claim
14 words
The circuit of claim 1, wherein the first dielectric layer comprises amorphous silicon dioxide.
Claim 8
Dependent Claim
21 words
The circuit of claim 1, wherein the passive circuit element has a surface area of not more than one square micrometer.
Claim 9
Dependent Claim
44 words
The circuit of claim 13, wherein: the circuit further comprise a second dielectric layer overlying and in direct contact with the substrate; and the first polycrystalline silicon layer overlies and is in direct contact with at least a portion of the second dielectric layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-18 | 1996-02-17 | 1996-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-18 | 2000-02-17 | 2000-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-18 | 2004-02-17 | 2004-08-18 | $7700.00 | Window Closed / Lapsed |