Image canceling mixer circuit on an integrated circuit chip

Claim 2

An image-rejecting mixer circuit on an integrated circuit chip, comprising: first and second mixers each receiving a radio frequency signal, the first mixer receiving a local-oscillator reference signal, the second mixer receiving the local-oscillator reference signal shifted in phase by 90 degrees, said first mixer producing a first mixed output and said second mixer producing a second mixed output; a phase-shift circuit coupled to the second mixer and receiving said second mixed output therefrom, said phase-shift circuit delaying the second mixed output signals an additional 90 degrees and including means for adjusting the phase angle of the signal output therefrom; and a summing circuit coupled to the first mixer and the 90 degree phase-shift circuit, the summing circuit combining in-phase components of said first mixed output from the first mixer with said second mixed output signals of the second mixer delayed by 180 degrees, to produce a combined signal which has image frequency components, said phase-shaft circuit comprising a unity gain transistor amplifier having a transistor with a base, a collector, and an emitter, a base circuit receiving the converted product signals from said second mixer, a collector to base capacitor, an emitter load including a fixed resistor, and a collector load including a fixed resistor in series with a diode-connected transistor, the adjusting means including an adjustable emitter load resistor, whereby a variation in emitter load current introduced by the adjustable resistor varies dynamic emitter resistance to compensate for production variations of the fixed resistors and produces an RC time constant which results in a 90 degree phase shift of the output signal, and whereby the image frequency components of the combined signals are substantially attenuated.

Claim 3

The mixer circuit of claim 1 further comprising a temperature compensating current source in the adjustable emitter load of the phase-shift circuit.

Claim 4

An integrated-circuit phase shift element comprising: a unity gain amplifier circuit having a transistor with a base receiving an input signal, a collector to base capacitor, an emitter load including a fixed resistor, and a collector load including a fixed resistor in series with a diode-connected transistor, the amplifier circuit having means for adjusting the phase angle of an output signal with respect to the input signal, the phase shift adjusting means including an adjustable emitter load resistor, whereby a variation in emitter load current introduced by the adjustable resistor varies dynamic emitter resistance to compensate for production variations of the fixed resistors and produces an RC time constant which results in a desired phase shift of the output signal with respect to the input signal, wherein collector load current tracks the varying emitter load current to preserve the unity gain of the amplifier circuit as the phase is varied.

Claim 5

An integrated-circuit phase shift element comprising: a unity gain amplifier circuit having a transistor with a base receiving an input signal, a collector to base capacitor, an emitter load including a fixed resistor, and a collector load including a fixed resistor in series with a diode-connected transistor, the amplifier circuit having means for adjusting the phase angle of an output signal with respect to the input signal, the phase shift adjusting means including an adjustable emitter load resistor, whereby a variation in emitter load current introduced by the adjustable resistor varies dynamic emitter resistance to compensate for production variations of the fixed resistors and produces an RC time constant which results in a desired phase shift of the output signal with respect to the input signal, wherein collector load current tracks the varying emitter load current to preserve the unity gain of the amplifier circuit as the phase is varied.

Claim 6

The integrated-circuit phase shift element of claim 3 further comprising a temperature compensating current source in the emitter load of the unity gain amplifier circuit.

Claim 7

An image canceling mixer circuit including means for generating a first in-phase reference frequency signal; means for generating a second reference frequency signal shifted in phase by 90° with respect to the first reference frequency signal; first means receiving a radio frequency input signal for mixing the input signal with the first reference frequency signal to generate an in-phase composite signal; second means receiving the radio frequency input signal for mixing the input signal with the second reference frequency signal to generate a quadrature composite signal; means coupled to the second mixing means for shifting the phase of the quadrature composite signal an additional 90° to generate a composite signal shifted in phase by 180° with respect to the in-phase composite signal; means for summing the in-phase composite signal and the 180° composite signal to generate an intermediate frequency signal output having attenuated image-frequency components, the improvement comprising: the phase shifting means including a unity gain amplifier circuit having an NPN transistor with a base receiving the quadrature composite signal, a collector to base capacitor, an emitter load including a fixed resistor, and a collector load including a fixed resistor in series with a diode-connected transistor, the amplifier circuit having means for adjusting the phase angle of the phase shift adjusting means and including an adjustable emitter load resistor, whereby a variation in the emitter load current introduced by the adjustable resistor varies dynamic emitter resistance to compensate for production variations of the fixed resistors and produces an RC time constant which results in a 90° phase shift of the output signal with respect to the input quadrature composite signal, the collector load current tracking the varying emitter load current to preserve the unity gain of the amplifier circuit as the phase is varied.

Claim 8

An image canceling mixer circuit including means for generating a first in-phase reference frequency signal; means for generating a second reference frequency signal shifted in phase by 90° with respect to the first reference frequency signal; first means receiving a radio frequency input signal for mixing the input signal with the first reference frequency signal to generate an in-phase composite signal; second means receiving the radio frequency input signal for mixing the input signal with the second reference frequency signal to generate a quadrature composite signal; means coupled to the second mixing means for shifting the phase of the quadrature composite signal an additional 90° to generate a composite signal shifted in phase by 180° with respect to the in-phase composite signal; means for summing the in-phase composite signal and the 180° composite signal to generate an intermediate frequency signal output having attenuated image-frequency components, the improvement comprising: the phase shifting means including a unity gain amplifier circuit having an NPN transistor with a base receiving the quadrature composite signal, a collector to base capacitor, an emitter load including a fixed resistor, and a collector load including a fixed resistor in series with a diode-connected transistor, the amplifier circuit having means for adjusting the phase angle of the phase shift adjusting means and including an adjustable emitter load resistor, whereby a variation in the emitter load current introduced by the adjustable resistor varies dynamic emitter resistance to compensate for production variations of the fixed resistors and produces an RC time constant which results in a 90° phase shift of the output signal with respect to the input quadrature composite signal, the collector load current tracking the varying emitter load current to preserve the unity gain of the amplifier circuit as the phase is varied.