High speed latching comparator using devices with negative impedance

Claim 1

A high speed latching comparator, comprising: a pair of latching devices characterized by higher and lower voltage regions of positive electrical impedance separated by negative electrical impedance, said latching devices triggering from their lower to their higher voltage regions of positive impedance in response to their currents exceeding a trigger level, and having respective input and output sides, a pair of hysteresis elements connected in circuit with said latching devices for maintaining said devices when triggered in their higher voltage regions of positive impedance at a lower voltage than the initial higher voltage region trigger voltage, a pair of impedance elements cross-coupling the input and output sides of said latching devices for enabling one latching device to be latched in its high voltage state while diverting current away form the non-latching device, thereby preventing the non-triggering latching device from latching in its high voltage region of positive impedance, first current source means for supplying a current, first steering circuit means coupled between said latching devices and said current source means for providing a differential current to said latching devices, said first steering circuit means comprising a pair of transistors differentially connected, with one transistor connected to each latching device, wherein one transistor is biased by an input signal and the other transistor is biased by a reference signal, wherein said differential current is proportional to the difference between said input signal and said reference signal, and a second current steering circuit coupled to said first steering circuit means for modifying said differential current between said latching devices such that one of the latching devices is triggered into its high voltage region of positive impedance.