US5138708A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital processor using current state comparison for providing fault tolerance
Assignee: Unisys Corp
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Filing: 1989-08-03
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Granted: 1992-08-11
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Expires: 2009-08-03
Abstract
Abstract A highly fault-tolerant processor is comprised of first and second central processing units (CPU) executing the same instruction sequence. Each CPU provides a state vector representing the current state thereof. The current state of each CPU is defined by the contents of a set of appropriate registers of the CPU after the CPU has completed execution of an instruction. The bits comprising the state vectors are compared by EXCLUSIVE OR gates, the outputs of which being ORed to provide a fail flag indicative of whether or not the state vectors agree with respect to each other. The state previous to the current state is stored external to the CPUs in a state image storage. The external image of the previous state is stored by pushing the existing contents of each of the registers in the set from one of the CPUs into the external image storage prior to the contents of the register being changed pursuant to the execution of the current instruction.
Inventors
- 👤 Newman A. Vosbury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:26
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1641; G06F11/165
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
406 words
A digital processor for providing fault tolerance, comprising first and second central processing units (CPU), said first and second CPUs being identical with respect to each other and adapted to execute the same sequence of instructions P 1 , P 2 , . . . , P I , . . . , P N , said first and second CPUs simultaneously executing the same instruction P I , each said CPU having a total current state S I after the execution of each instruction P I and a total prior state S I-1 after the execution of each instruction P I-1 , each said CPU providing a state vector signal representative of the total current state S I thereof after the execution of each said instruction P I , said state vector signal from said first CPU being provided from a first set of points internal to said first CPU, said first set of points completely defining the state of said first CPU, said state vector signal from said second CPU being provided from a second set of points internal to said second CPU, said second set of points completely defining the state of said second CPU, said first set of points internal to said first CPU being identical to said second set of points internal to said second CPU, comparison means responsive to said state vector signals from said first and second CPUs for comparing said state vector signals from said first and second CPUs after execution of each said instruction P I for providing a fail flag signal representative of processor failure when said state vector signals disagree, state image storage means coupled to said first CPU for storing a state image signal representative of the total prior state S I-1 of said first CPU after the execution of each said instruction P I-1 , said state image signal being identical to said state vector signal from said first CPU, means responsive to said fail flag signal for halting instruction execution of said processor when said fail flag signal is representative of said processor failure, and means responsive to said state image signal for providing said state image signal for use external to said processor when said fail flag signal is representative of said processor failure, so that said state image signal can be used to resume processing from a state just prior to an instruction during execution of which said failure occurred.
Claim 2
Dependent Claim
406 words
A digital processor for providing fault tolerance, comprising first and second central processing units (CPU), said first and second CPUs being identical with respect to each other and adapted to execute the same sequence of instructions P 1 , P 2 , . . . , P I , . . . , P N , said first and second CPUs simultaneously executing the same instruction P I , each said CPU having a total current state S I after the execution of each instruction P I and a total prior state S I-1 after the execution of each instruction P I-1 , each said CPU providing a state vector signal representative of the total current state S I thereof after the execution of each said instruction P I , said state vector signal from said first CPU being provided from a first set of points internal to said first CPU, said first set of points completely defining the state of said first CPU, said state vector signal from said second CPU being provided from a second set of points internal to said second CPU, said second set of points completely defining the state of said second CPU, said first set of points internal to said first CPU being identical to said second set of points internal to said second CPU, comparison means responsive to said state vector signals from said first and second CPUs for comparing said state vector signals from said first and second CPUs after execution of each said instruction P I for providing a fail flag signal representative of processor failure when said state vector signals disagree, state image storage means coupled to said first CPU for storing a state image signal representative of the total prior state S I-1 of said first CPU after the execution of each said instruction P I-1 , said state image signal being identical to said state vector signal from said first CPU, means responsive to said fail flag signal for halting instruction execution of said processor when said fail flag signal is representative of said processor failure, and means responsive to said state image signal for providing said state image signal for use external to said processor when said fail flag signal is representative of said processor failure, so that said state image signal can be used to resume processing from a state just prior to an instruction during execution of which said failure occurred.
Claim 3
Dependent Claim
43 words
The processor of claim 1 wherein said comparison means comprises EXCLUSIVE OR gate means responsive to said state vector signals from said first and second CPUs, and OR gate means coupled to said EXCLUSIVE OR gate means for providing said fail flag signal.
Claim 4
Dependent Claim
93 words
The processor of claim 1 wherein said first CPU includes registers internal thereto that completely define the state of said first CPU, said total current state S I being represented by the contents of said registers internal to said first CPU, said registers providing said first set of points, and said second CPU includes registers internal thereto that completely define the state of said second CPU, said total current state S I being represented by the contents of said registers internal to said second CPU, said registers providing said second set of points.
Claim 5
Dependent Claim
37 words
The processor of claim 3 wherein said state image signal stored in said state image storage means comprises existing contents of each said register when said register is written into pursuant to execution of each said instruction.
Claim 6
Dependent Claim
16 words
The processor of claim 1 wherein said means responsive to said fail flag comprises interrupt means.
Claim 7
Dependent Claim
25 words
The processor of claim 1 wherein said means for providing said state image signal comprises an external bus coupled to said state image storage means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |