US5138707A
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Method of operating a timer in a digital data processing system
Assignee: International Business Machines Corp
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Filing: 1989-09-13
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Granted: 1992-08-11
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Expires: 2009-09-13
Abstract
Abstract A method of operating a timer mechanism in a digital data processing system is described in which the contents of at least one timer register is updated by a predetermined time increment during each of successive periodic update cycles. Each update cycle includes a predetermined number of operating cycles of the data processing system. During each update cycle, the contents of an adjustment register is circularly shifted by one bit position and if the bit value at a particular position in this adjustment register has a predetermined binary value during an update cycle, then actual updating of the timer register is omitted during a related update cycle.
Inventors
- 👤 Wilhelm Haller
- 👤 Johann Hajdu
- 👤 Klaus J. Getzlaff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:02
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/662; G; G06; G06F; G06F1/00; G06F1/04; G06F1/14
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
302 words
A method for maintaining a time value in a digital system which generates periodic clock signals, said time value being updatable in increments, said method comprising the steps of: generating periodic timing signals based on said clock signals, the timing signal period being shorter than the time value increment, said timing signal period being an integral multiple of the clock signal period but said clock signal period not being an integral submultiple of the time value increment; providing a shift register which has a multiplicity of actual bit positions, said shift register circulating binary control bits through said actual bit positions one or more actual cycles per shift register cycle to yield a total number of actual bit position shifts per shift register cycle such that a combined duration of said total number of said timing signal periods is an integral multiple of said time value increment; loading a first number of said actual bit positions of said shift register with control bits of a first binary level and loading a second number of said actual bit positions of said shift register with control bits of a second binary level, a combined duration of said total number of said timing signal periods being equal to said second number times said time value increment; shifting said shift register with each of said periodic timing signals; incrementing said time value each time a control bit of said second binary level is shifted to a certain position in said shift register; and preventing said time value from being incremented each time a control bit of said first binary level is shifted to said certain position in said shift register, whereby when said total number of timing signals has occurred the resultant time value equals the combined duration of said total number of timing signal periods.
Claim 2
Independent Claim
302 words
A method for maintaining a time value in a digital system which generates periodic clock signals, said time value being updatable in increments, said method comprising the steps of: generating periodic timing signals based on said clock signals, the timing signal period being shorter than the time value increment, said timing signal period being an integral multiple of the clock signal period but said clock signal period not being an integral submultiple of the time value increment; providing a shift register which has a multiplicity of actual bit positions, said shift register circulating binary control bits through said actual bit positions one or more actual cycles per shift register cycle to yield a total number of actual bit position shifts per shift register cycle such that a combined duration of said total number of said timing signal periods is an integral multiple of said time value increment; loading a first number of said actual bit positions of said shift register with control bits of a first binary level and loading a second number of said actual bit positions of said shift register with control bits of a second binary level, a combined duration of said total number of said timing signal periods being equal to said second number times said time value increment; shifting said shift register with each of said periodic timing signals; incrementing said time value each time a control bit of said second binary level is shifted to a certain position in said shift register; and preventing said time value from being incremented each time a control bit of said first binary level is shifted to said certain position in said shift register, whereby when said total number of timing signals has occurred the resultant time value equals the combined duration of said total number of timing signal periods.
Claim 3
Dependent Claim
47 words
A method in accordance with claim 1 wherein said total number of actual bit position shifts per shift register cycle is equal to a number of actual bit positions in said shift register which store said control bits that increment or prevent incrementing of said time value.
Claim 4
Dependent Claim
102 words
A method in accordance with claim 1 wherein said total number of bit position shifts per shift register cycle is an integral multiple greater than one of a number of actual bit positions in said shift register which store said control bits that increment or prevent incrementing of said time value, and each of said control bits in said actual bit positions is circularly shifted a plurality of actual cycles through said shift register during each shift register cycle such that each of said control bits increments or prevents incrementing of said time value a plurality of times per shift register cycle.
Claim 5
Dependent Claim
180 words
A method in accordance with claim 3 wherein said circulation of said control bits the plurality of actual cycles per shift register cycle results in a time value which approximates the combined duration of a number of timing signal periods, which number is equal to a number of actual bit positions times the plurality of actual cycles that said control bits are circularly shifted per shift register cycle; and said shift register further comprises additional actual bit positions which store additional control bits of said second and first binary levels that increment or prevent incrementing, respectfully, of said time value, the additional control bits being circularly shifted a different number of actual cycles than said plurality during each of said shift register cycles such that each of said additional control bits increments or prevents incrementing of said time value said different number of times per shift register cycle and at the end of said shift register cycle said time value equals a combined duration of a total number of shifts in said shift register cycle times the timing signal period.
Claim 6
Dependent Claim
13 words
A method in accordance with claim 4 wherein said different number is one.
Claim 7
Dependent Claim
50 words
A method in accordance with claim 1 wherein said first number is an integer greater than one, said second number is an integer greater than one and said control bits of said first binary level are interspersed with said control bits of said second binary level in said shift register.
Claim 8
Dependent Claim
293 words
A digital system which generates periodic clock signals and maintains a time value, said time value being updatable in increments, said system comprising: means for generating periodic timing signals based on said clock signals, the timing signal period being shorter than the time value increment, said timing signal period being an integral multiple of the clock signal period but said clock signal period not being an integral submultiple of the time value increment; a shift register which has a multiplicity of actual bit positions, said shift register circulating binary control bits through said actual bit positions one or more actual cycles per shift register cycle to yield a total number of actual bit position shifts per shift register cycle such that a combined duration of said total number of said timing signal periods is an integral multiple of said time value increment; and means for loading a first number of said actual bit positions of said shift register with control bits of a first binary level and loading a second number of said actual bit positions of said shift register with control bits of a second binary level, a combined duration of said total number of said timing signal periods being equal to said second number times said time value increment; and wherein said shift register is coupled to the generating means to receive said periodic timing signals and is shifted with each of said periodic timing signals; and further comprising means for incrementing said time value each time a control bit of said second binary level is shifted to a certain position in said shift register whereby when said total number of timing signals has occurred the resultant time value equals the combined duration of said total number of timing signal periods.
Claim 9
Dependent Claim
293 words
A digital system which generates periodic clock signals and maintains a time value, said time value being updatable in increments, said system comprising: means for generating periodic timing signals based on said clock signals, the timing signal period being shorter than the time value increment, said timing signal period being an integral multiple of the clock signal period but said clock signal period not being an integral submultiple of the time value increment; a shift register which has a multiplicity of actual bit positions, said shift register circulating binary control bits through said actual bit positions one or more actual cycles per shift register cycle to yield a total number of actual bit position shifts per shift register cycle such that a combined duration of said total number of said timing signal periods is an integral multiple of said time value increment; and means for loading a first number of said actual bit positions of said shift register with control bits of a first binary level and loading a second number of said actual bit positions of said shift register with control bits of a second binary level, a combined duration of said total number of said timing signal periods being equal to said second number times said time value increment; and wherein said shift register is coupled to the generating means to receive said periodic timing signals and is shifted with each of said periodic timing signals; and further comprising means for incrementing said time value each time a control bit of said second binary level is shifted to a certain position in said shift register whereby when said total number of timing signals has occurred the resultant time value equals the combined duration of said total number of timing signal periods.
Claim 10
Dependent Claim
45 words
A system in accordance with claim 7 wherein said total number of actual bit position shifts per shift register cycle is equal to a number of actual bit positions in said shift register which store said control bits of said first and second binary levels.
Claim 11
Dependent Claim
101 words
A system in accordance with claim 7 wherein said total number of bit position shifts per shift register cycle is an integral multiple greater than one of a number of actual bit positions in said shift register which store said control bits of said first and second binary levels, and each of said control bits in said actual bit positions is circularly shifted a plurality of actual cycles through said shift register during each shift register cycle such that each of said control bits of said second binary level increments said time value a plurality of times per shift register cycle.
Claim 12
Dependent Claim
171 words
A system in accordance with claim 9 wherein said circulation of said control bits the plurality of actual cycles per shift register cycle results in a time value which approximates the combined duration of a number of timing signal periods, which number is equal to a number of said actual bit positions times the plurality of actual cycles that said control bits are circularly shifted per shift register cycle; and said shift register further comprises additional actual bit positions which store additional control bits of said first and second binary levels, the additional control bits being circularly shifted a different number of actual cycles than said plurality during each of said shift register cycles such that each of said additional control bits of said second binary level increments said time value said different number of times per shift register cycle and at the end of said shift register cycle said time value equals the duration of a total number of shifts in said shift register cycle times the timing signal period.
Claim 13
Dependent Claim
13 words
A system in accordance with claim 10 wherein said different number is one.
Claim 14
Dependent Claim
50 words
A system in accordance with claim 7 wherein said first number is an integer greater than one, said second number is an integer greater than one and said control bits of said first binary level are interspersed with said control bits of said second binary level in said shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |