US5138637A
Expired / Lapsed
US
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First-in-first-out buffer
Assignee: Fujitsu Services Ltd
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Filing: 1991-09-16
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Granted: 1992-08-11
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Expires: 2011-09-16
Abstract
Abstract A first-in-first-out buffer is described for transferring data between two asynchronous clock regimes. The buffer comprises a first register file, for transferring data from the slow to the fast clock regime, and a second register file for transferring data in the opposite direction. The write addresses for the first register file are produced by a counter in the slow clock regime, and converted back to standard binary, and a predetermined offset is added to the result, so as to produce a read address for the first register file. This is also used as the write address for the second register file. The read address for the second register file is produced by adding a predetermined offset to the output of the counter. Thus, the read and write addresses of the two register files are always in a fixed relationship, so that it is not necessary to provide special logic for detecting the buffer full and buffer empty conditions.
Inventors
- 👤 Trevor R. Fox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:13
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/065; G06F2205/00; G06F2205/10; G06F2205/102
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
97 words
A first-in-first out buffer for transferring data from a first clock regime to a second, asynchronous clock regime, the buffer comprising: a) a plurality of data storage locations, b) a write counter, synchronised to the first clock regime, for producing a first address, the first address being used to select one of the storage of locations to receive data from the first clock regime, and c) means for deriving a second address from the first address, and for using the second address to select one of the storage locations to supply data to the second clock regime.
Claim 2
Dependent Claim
97 words
A first-in-first out buffer for transferring data from a first clock regime to a second, asynchronous clock regime, the buffer comprising: a) a plurality of data storage locations, b) a write counter, synchronised to the first clock regime, for producing a first address, the first address being used to select one of the storage of locations to receive data from the first clock regime, and c) means for deriving a second address from the first address, and for using the second address to select one of the storage locations to supply data to the second clock regime.
Claim 3
Dependent Claim
170 words
A first-in-first-out buffer for transferring data between a first clock regime and a second, asynchronous clock regime, the buffer comprising: a) first and second register files, each of which comprises a plurality of data storage locations, b) a write counter, synchronised to the first clock regime, for producing a first address, the first address being used to select one of the storage locations in the first register file to receive data from the first clock regime, c) means for deriving a second address from the first address, the second address being used to select one of the storage locations in the first register file to supply data to the second clock regime, and to select one of the storage locations in the second register file to receive data from the second clock regime, and d) means for deriving a third address from the first address, the third address being used to select one of the storage locations in the second register file to supply data to the first clock regime.
Claim 4
Dependent Claim
170 words
A first-in-first-out buffer for transferring data between a first clock regime and a second, asynchronous clock regime, the buffer comprising: a) first and second register files, each of which comprises a plurality of data storage locations, b) a write counter, synchronised to the first clock regime, for producing a first address, the first address being used to select one of the storage locations in the first register file to receive data from the first clock regime, c) means for deriving a second address from the first address, the second address being used to select one of the storage locations in the first register file to supply data to the second clock regime, and to select one of the storage locations in the second register file to receive data from the second clock regime, and d) means for deriving a third address from the first address, the third address being used to select one of the storage locations in the second register file to supply data to the first clock regime.
Claim 5
Dependent Claim
54 words
A buffer according to Claim 1 wherein the means for deriving the second address from the first address comprises means for encoding the first address in a Gray code, means for resynchronising said Gray code to the second clock regime, and means for decoding the resynchronised Gray code back into a conventional binary code.
Claim 6
Dependent Claim
52 words
A buffer according to Claim 3 further including means for comparing said second address, at each clock beat of the second clock regime, with the value of said second address in the previous clock beat of the second clock regime, and for producing a data available signal when said values are different.
Claim 7
Dependent Claim
54 words
A buffer according to claim 2 wherein the means for deriving the second address from the first address comprises means for encoding the first address in a Gray code, means for resynchronising said Gray code to the second clock regime, and means for decoding the resynchronised Gray code back into a conventional binary code.
Claim 8
Dependent Claim
23 words
A buffer according to claim 1 wherein the means for deriving the second address comprises an adder for adding a predetermined offset value.
Claim 9
Dependent Claim
27 words
A buffer according to claim 2, wherein said means for deriving the third address comprises an adder for adding a predetermined offset value to said first address.
Claim 10
Dependent Claim
26 words
A buffer according to claim 5, including means for producing a write enable signal for the second register file whenever the data enable signal is true.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |