US5138320A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Skew code generator for measuring pulses width using a delay line
Assignee: Zenith Electronics LLC
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Filing: 1990-11-14
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Granted: 1992-08-11
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Expires: 2010-11-14
Abstract
Abstract A skew code generator for digitally quantizing the width of a pulse. A series connected string of identical voltage controllable delay elements is supplied with the pulse, which is sensed as it passes through each of the delay elements. Output signals are developed in response to the leading edge of the pulse and are latched in response to the trailing edge of the pulse. An encoder generates a binary output from the latched output signals, which is indicative of the width of the pulse.
Inventors
- 👤 Duc Ngo
- 👤 Timothy J. Donovan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:41
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; G; G01; G01R; G01R25/00; H03K5/133; H03K2005/00013; H03K2005/00078; H03K2005/00097; H03K2005/00104; H03K2005/0015; H03K2005/00189
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
83 words
A skew code generator for digitally quantizing the width of a pulse comprising: a serially connected plurality of substantially identical voltage controllable delay elements; means for applying a control voltage to said voltage controllable delay elements to determine their delays; means for supplying a pulse to said serially connected delay elements; means for sensing passage of said pulse in said serially connected delay elements and for developing output signals responsive thereto; and means for generating a digital output responsive to said output signals.
Claim 2
Dependent Claim
83 words
A skew code generator for digitally quantizing the width of a pulse comprising: a serially connected plurality of substantially identical voltage controllable delay elements; means for applying a control voltage to said voltage controllable delay elements to determine their delays; means for supplying a pulse to said serially connected delay elements; means for sensing passage of said pulse in said serially connected delay elements and for developing output signals responsive thereto; and means for generating a digital output responsive to said output signals.
Claim 3
Dependent Claim
43 words
The generator of claim 1 wherein said pulse has a leading edge and a trailing edge, and wherein said output signals are developed in response to said leading edge, and further including means for latching said output signals responsive to said trailing edge.
Claim 4
Dependent Claim
16 words
The generator of claim 2, further including phase locked loop means for developing said control voltage.
Claim 5
Dependent Claim
24 words
The generator of claim 3 wherein said digital output generating means includes an encoder coupled to said latching means and receiving said output signals.
Claim 6
Dependent Claim
33 words
The generator of claim 4 wherein said phase locked loop means includes delay means comprising at least one other delay element substantially identical to said delay elements and supplied with said control voltage.
Claim 7
Dependent Claim
117 words
A skew code generator for digitally quantizing the width of a pulse comprising: a serially connected plurality of substantially identical voltage controllable delay elements; phase locked loop means for developing a control voltage for each of said voltage controllable delay elements to determine their delays; means for supplying a pulse having a leading edge and a trailing edge to said serially connected delay elements; means for sensing passage of said leading edge in said delay elements and for developing output signals responsive thereto; means for latching said output signals responsive to said trailing edge; and encoding means coupled to said latching means and receiving said output signals for generating a digital output responsive to said output signals.
Claim 8
Dependent Claim
117 words
A skew code generator for digitally quantizing the width of a pulse comprising: a serially connected plurality of substantially identical voltage controllable delay elements; phase locked loop means for developing a control voltage for each of said voltage controllable delay elements to determine their delays; means for supplying a pulse having a leading edge and a trailing edge to said serially connected delay elements; means for sensing passage of said leading edge in said delay elements and for developing output signals responsive thereto; means for latching said output signals responsive to said trailing edge; and encoding means coupled to said latching means and receiving said output signals for generating a digital output responsive to said output signals.
Claim 9
Dependent Claim
35 words
The generator of claim 6 wherein said phase locked loop means includes delay means comprising at least one other delay element that is substantially identical to said delay elements and supplied with said control voltage.
References Cited (Backward Citations)
US4772937A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |