Solid state switch with last state memory

Claim 2

A solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption, said switch comprising: output driver means formed of at least one N-channel MOS field-effect transistor having its drain connected to a first output terminal and its source connected to a second output terminal; holding means formed of a holding capacitor having its one end connected to the gate of said field-effect transistor and its other end connected to a ground potential; a charging resistor having its one end connected to the one end of said holding capacitor; a bipolar transistor having its collector connected to the one end of said holding capacitor, its emitter connected to the ground potential, and its base coupled to receive a logic control signal; means interconnected between a power supply voltage source and the other end of said charging resistor for preventing leakage of said holding capacitor; and said holding capacitor retaining the last state between the first and second output terminals in the event of a loss of the power supply voltage source.

Claim 3

A solid state switch as claimed in claim 1, wherein said means for preventing leakage of the holding capacitor comprises at least one diode having its anode connected to the power supply voltage source and its cathode connected to the other end of said charging resistor.

Claim 4

A solid state switch as claimed in claim 2, wherein said diode is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 5

A solid state switch as claimed in claim 1, wherein said means for preventing the leakage of the holding capacitor comprises a plurality of series-connected diodes having its anode end connected to the power supply voltage source and its cathode end connected to the other end of said charging resistor.

Claim 6

A solid state switch as claimed in claim 4, wherein each of said diodes is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 7

A solid state switch as claimed in claim 1, further comprising switching controller circuit means for generating said logic control signal.

Claim 8

A solid state switch as claimed in claim 6, wherein said switching controller circuit means is comprised of a light-emitting diode and a phototransistor responsive to said light-emitting diode for generating said logic control signal at its collector.

Claim 9

A solid state switch as claimed in claim 7, further comprising a current-limiting resistor connected between the collector of said phototransistor and the base of said bipolar transistor.

Claim 10

A solid state switch as claimed in claim 1, wherein said output driver means is comprised of a plurality of N-channel MOS field-effect transistors connected whose gates are together so as to provide multiple switch poles.

Claim 11

A single-pole, double throw solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption, said switch comprising; output driver means formed of at least one pair of first and second N-channel MOS field-effect transistors, said first field-effect transistor having its drain connected to a first output terminal and its source connected to a common output terminal, said second field-effect transistor having its drain connected to a second output terminal and its source connected to the common output terminal; first holding means formed of a first holding capacitor having its one end connected to a gate of said first field-effect transistor and its other end connected to a ground potential; a first charging resistor having its one end connected to one end of said first holding capacitor; a first bipolar transistor having its collector connected to one end of said first holding capacitor, its emitter connected to the ground potential, and its base coupled to receive a first logic control signal; second holding means formed of a second holding capacitor having its one end connected to a gate of said second field-effect transistor and its other end connected to a ground potential; a second charging resistor having its one end connected to one end of said second holding capacitor; a second bipolar transistor having its collector connected to one end of said second holding capacitor, its emitter connected to the ground potential, and its base coupled to receive a second logic control signal; means interconnected between a power supply voltage source and the other ends of said first and second charging resistors for preventing leakage of said first and second holding capacitors; and said first holding capacitor retaining the last state between the first and common output terminals and said second holding capacitor retaining the last state between the second and common output terminals in the event of a loss of the power supply voltage source.

Claim 12

A single-pole, double throw solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption, said switch comprising; output driver means formed of at least one pair of first and second N-channel MOS field-effect transistors, said first field-effect transistor having its drain connected to a first output terminal and its source connected to a common output terminal, said second field-effect transistor having its drain connected to a second output terminal and its source connected to the common output terminal; first holding means formed of a first holding capacitor having its one end connected to a gate of said first field-effect transistor and its other end connected to a ground potential; a first charging resistor having its one end connected to one end of said first holding capacitor; a first bipolar transistor having its collector connected to one end of said first holding capacitor, its emitter connected to the ground potential, and its base coupled to receive a first logic control signal; second holding means formed of a second holding capacitor having its one end connected to a gate of said second field-effect transistor and its other end connected to a ground potential; a second charging resistor having its one end connected to one end of said second holding capacitor; a second bipolar transistor having its collector connected to one end of said second holding capacitor, its emitter connected to the ground potential, and its base coupled to receive a second logic control signal; means interconnected between a power supply voltage source and the other ends of said first and second charging resistors for preventing leakage of said first and second holding capacitors; and said first holding capacitor retaining the last state between the first and common output terminals and said second holding capacitor retaining the last state between the second and common output terminals in the event of a loss of the power supply voltage source.

Claim 13

A solid state switch as claimed in claim 10, wherein said means for preventing leakage of the first and second holding capacitors comprises at least one first and second diodes each having its anode connected to the power supply voltage source and its cathode connected to the other end of said respective first and second charging resistors.

Claim 14

A solid state switch as claimed in claim 11, wherein each of said first and second diodes is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 15

A solid state switch as claimed in claim 10, wherein said means for preventing the leakage of the first and second holding capacitors comprises a plurality of series-connected first and second diodes each having its anode end connected to the power supply voltage source and its cathode end connected to the other end of said respective first and second charging resistors.

Claim 16

A solid state switch as claimed in claim 13, wherein each of said plurality of first and second diodes is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 17

A solid state switch as claimed in claim 10, further comprising switching controller circuit means for generating said first and second logic control signals.

Claim 18

A solid state switch as claimed in claim 15, wherein said switching controller means is comprised of a light-emitting diode and a phototransistor responsive to said light-emitting diode for generating said first and second logic control signals at respective first and second outputs of said switching controller circuit means.

Claim 19

A solid state switch as claimed in claim 16, further comprising first and second current-limiting resistors connected between the first and second outputs of said switching controller circuit means and the bases of said first and second bipolar transistors.

Claim 20

A solid state switch as claimed in claim 10, wherein said output driver means is comprised of a plurality of said first and second N-channel MOS field-effect transistors, said plurality of said first N-channel MOS field-effect transistors having their gates connected together and said plurality of said second N-channel MOS field-effect transistors having their gates connected together so as to provide multiple switch poles.

Claim 21

A single-pole, double throw solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption, said switch comprising; output driver means formed of at least one pair of first and second N-channel MOS field-effect transistors, said first field-effect transistor having its drain connected to a first output terminal and its source connected to a common output terminal, said second field-effect transistor having its drain connected to a second output terminal and its source connected to the common output terminal; first bipolar transistor having its collector connected to a gate of said first field-effect transistor, its emitter connected to a ground potential, and its base coupled to receive a first logic control signal; first holding means formed of a first holding capacitor having a first end and a second end connected to the ground potential; a first charging resistor having its one end connected to the first end of said first holding capacitor; second bipolar transistor having its collector connected to a gate of said second field-effect transistor, its emitter connected to the ground potential, and its base coupled to receive a second logic control signal; second holding means formed of a second holding capacitor having a first end and a second end connected to the ground potential; a second charging resistor having its one end connected to the first end of said second holding capacitor; means interconnected between a power supply voltage source and the other ends of said first and second charging resistors for preventing leakage of said first and second holding capacitors; first isolation diode having its anode connected to the first end of said first holding capacitor and its cathode coupled to the collector of said first bipolar transistor, and to a first output of said means for preventing leakage of said first and second holding capacitors; second isolation diode having its anode connected to the first end of said second holding capacitor and its cathode coupled to the collector of said second bipolar transistor, and to a second output of said means for preventing leakage of said first and second holding capacitors; and said first capacitor retaining the last state between said first and common output terminals and said second holding capacitor retaining the last state between the second and common output terminals in the event of a loss of the power supply voltage source.

Claim 22

A single-pole, double throw solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption, said switch comprising; output driver means formed of at least one pair of first and second N-channel MOS field-effect transistors, said first field-effect transistor having its drain connected to a first output terminal and its source connected to a common output terminal, said second field-effect transistor having its drain connected to a second output terminal and its source connected to the common output terminal; first bipolar transistor having its collector connected to a gate of said first field-effect transistor, its emitter connected to a ground potential, and its base coupled to receive a first logic control signal; first holding means formed of a first holding capacitor having a first end and a second end connected to the ground potential; a first charging resistor having its one end connected to the first end of said first holding capacitor; second bipolar transistor having its collector connected to a gate of said second field-effect transistor, its emitter connected to the ground potential, and its base coupled to receive a second logic control signal; second holding means formed of a second holding capacitor having a first end and a second end connected to the ground potential; a second charging resistor having its one end connected to the first end of said second holding capacitor; means interconnected between a power supply voltage source and the other ends of said first and second charging resistors for preventing leakage of said first and second holding capacitors; first isolation diode having its anode connected to the first end of said first holding capacitor and its cathode coupled to the collector of said first bipolar transistor, and to a first output of said means for preventing leakage of said first and second holding capacitors; second isolation diode having its anode connected to the first end of said second holding capacitor and its cathode coupled to the collector of said second bipolar transistor, and to a second output of said means for preventing leakage of said first and second holding capacitors; and said first capacitor retaining the last state between said first and common output terminals and said second holding capacitor retaining the last state between the second and common output terminals in the event of a loss of the power supply voltage source.

Claim 23

A solid state switch as claimed in claim 19, wherein said means for preventing leakage of the first and second holding capacitors comprises at least one first and second diodes each having its anode connected to the power supply source and its cathode connected to the other end of said respective first and second charging resistors.

Claim 24

A solid state switch as claimed in claim 20, wherein each of said first and second diodes is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 25

A solid state switch as claimed in claim 19, wherein said means for preventing the leakage of the first and second holding capacitors comprises a plurality of series-connected first and second diodes each having its anode end connected to the power supply voltage source and its cathode end connected to the other end of said respective first and second charging resistors.

Claim 26

A solid state switch as claimed in claim 22, wherein each of said plurality of first and second diodes is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 27

A solid state switch as claimed in claim 19, further comprising switching controller circuit means for generating said first and second logic control signals.

Claim 28

A solid state switch as claimed in claim 24, wherein said switching controller means is comprised of a light-emitting diode and a phototransistor responsive to said light-emitting diode for generating said first and second logic control signals at respective first and second outputs of said switching controller circuit means.

Claim 29

A solid state switch as claimed in claim 24, further comprising first and second current-limiting resistors connected between the first and second outputs of said switching controller circuit means and the bases of said first and second bipolar transistors.

Claim 30

A solid state switch as claimed in claim 19, wherein said output driver means is comprised of a plurality of said first and second N-channel MOS field-effect transistors, said plurality of said first N-channel MOS field-effect transistors having their gates connected together and said plurality of said second N-channel MOS field-effect transistors having their gates connected together so as to provide multiple switch poles.

Claim 31

A single-pole, double throw solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption, said switch comprising; output driver means formed of at least one pair of first and second N-channel MOS field-effect transistors, said first field-effect transistor having its drain connected to a first output terminal and its source connected to a common output terminal, said second field-effect transistor having its drain connected to a second output terminal and its source connected to the common output terminal; a first bipolar transistor having a collector, base and emitter connection to ground; a second bipolar transistor having its collector coupled to a gate of said first field-effect transistor and its emitter connected to a ground potential; first holding means formed of a first holding capacitor having a first end connected to the collector of said first bipolar transistor and a second end connected to the ground potential; a first charging resistor having its one end connected to the first end of said first holding capacitor and its other end coupled to a power supply voltage source; a third bipolar transistor having its collector coupled to the bases of said first and second bipolar transistors, its emitter connected to the ground potential, and its base coupled to receive a first logic control signal; a fourth bipolar transistor having a collector, base and emitter connected to ground; a fifth bipolar transistor having its collector coupled to the gate of said second field-effect transistor and its emitter connected to the ground potential; second holding means formed of a second holding capacitor having a first end connected to the collector of said fourth bipolar transistor and a second end connected to the ground potential; a second charging resistor having its one end connected to the first end of said second holding capacitor and its other end coupled to the power supply voltage source; a sixth bipolar transistor having its collector coupled to the bases of said fourth and fifth bipolar transistors, its emitter connected to the ground potential, and its base coupled to receive a second logic control signal. first feedback control means connected between the first end of said second holding capacitor and the base of said third bipolar transistor; second feedback control means connected between the first end of said first holding capacitor and the base of said sixth bipolar transistor; and said first and second feedback control means rendering a "break-before-make" function across the first and second output terminals.

Claim 32

A single-pole, double throw solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption, said switch comprising; output driver means formed of at least one pair of first and second N-channel MOS field-effect transistors, said first field-effect transistor having its drain connected to a first output terminal and its source connected to a common output terminal, said second field-effect transistor having its drain connected to a second output terminal and its source connected to the common output terminal; a first bipolar transistor having a collector, base and emitter connection to ground; a second bipolar transistor having its collector coupled to a gate of said first field-effect transistor and its emitter connected to a ground potential; first holding means formed of a first holding capacitor having a first end connected to the collector of said first bipolar transistor and a second end connected to the ground potential; a first charging resistor having its one end connected to the first end of said first holding capacitor and its other end coupled to a power supply voltage source; a third bipolar transistor having its collector coupled to the bases of said first and second bipolar transistors, its emitter connected to the ground potential, and its base coupled to receive a first logic control signal; a fourth bipolar transistor having a collector, base and emitter connected to ground; a fifth bipolar transistor having its collector coupled to the gate of said second field-effect transistor and its emitter connected to the ground potential; second holding means formed of a second holding capacitor having a first end connected to the collector of said fourth bipolar transistor and a second end connected to the ground potential; a second charging resistor having its one end connected to the first end of said second holding capacitor and its other end coupled to the power supply voltage source; a sixth bipolar transistor having its collector coupled to the bases of said fourth and fifth bipolar transistors, its emitter connected to the ground potential, and its base coupled to receive a second logic control signal. first feedback control means connected between the first end of said second holding capacitor and the base of said third bipolar transistor; second feedback control means connected between the first end of said first holding capacitor and the base of said sixth bipolar transistor; and said first and second feedback control means rendering a "break-before-make" function across the first and second output terminals.

Claim 33

A solid state switch as claimed in claim 28, further comprising first and second diodes each having its anode connected to the power supply voltage source and its cathode connected to the other end of said respective first and second charging resistors.

Claim 34

A solid state switch as claimed in claim 29, wherein each of said first and second diodes is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 35

A solid state switch as claimed in claim 28, further comprising a plurality of series-connected first and second diodes each having its anode end connected to the power supply voltage source and its cathode end connected to the other end of said respective first and second charging resistors.

Claim 36

A solid state switch as claimed in claim 31, wherein each of said plurality of first and second diodes is formed of a transistor having its base and collector connected together to form the anode and its emitter defining the cathode.

Claim 37

A solid state switch as claimed in claim 28, further comprising switching controller circuit means for generating said first and second logic control signals.

Claim 38

A solid state switch as claimed in claim 28, wherein said switching controller means is comprised of a light-emitting diode and a phototransistor responsive to said light-emitting diode for generating said first and second logic control signals at respective first and second outputs of said switching controller circuit means.

Claim 39

A solid state switch as claimed in claim 34, further comprising first and second current-limiting resistors connected between the first and second outputs of said switching controller circuit means and the bases of said first and second bipolar transistors.

Claim 40

A solid state switch as claimed in claim 28, wherein said output driver means is comprised of a plurality of said first and second N-channel MOS field-effect transistors, said plurality of said first N-channel MOS field-effect transistors having their gates connected together and said plurality of said second N-channel MOS field-effect transistors having their gates connected together so as to provide multiple switch poles.

Claim 41

A single-pole, double throw solid state switch as claimed in claim 28, wherein said first feedback control means comprises a third MOS field-effect transistor.

Claim 42

A single-pole, double throw solid state switch as claimed in claim 37, wherein said second feedback control means comprises a fourth MOS field-effect transistor.