US5136255A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier circuit
Assignee: Texas Instruments Inc
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Filing: 1991-06-28
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Granted: 1992-08-04
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Expires: 2011-06-28
Abstract
Abstract An amplification circuit in accordance with the present invention includes an amplifier comprising four inputs. Each of the four inputs is operable to receive a respective analog signal and a respective DC bias signal. Also included is supply circuitry for providing a first and second controlled DC bias signal. Each of the DC bias signals is operable to couple to selected ones of the four inputs of the amplifier.
Inventors
- 👤 John W. Fattaruso
- 👤 James R. Hellums
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:39
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; G06G7/1865; H03F3/26; H03F3/265; H03F3/45475
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
115 words
A method of providing first and second DC bias signals and first and second analog signals to an amplification circuit comprising an amplifier, the method comprising: coupling the first and second analog signals to respective first and second capacitors during a first clock cycle; coupling the first DC bias signal to the first and second capacitors during the first clock cycle; coupling the first and second analog signals to respective third and fourth capacitors during the first clock cycle; and coupling the second DC bias signal to the third and fourth capacitors during the first clock cycle, wherein the first, second, third and fourth capacitors are each coupled to a respective input of the amplifier.
Claim 2
Independent Claim
115 words
A method of providing first and second DC bias signals and first and second analog signals to an amplification circuit comprising an amplifier, the method comprising: coupling the first and second analog signals to respective first and second capacitors during a first clock cycle; coupling the first DC bias signal to the first and second capacitors during the first clock cycle; coupling the first and second analog signals to respective third and fourth capacitors during the first clock cycle; and coupling the second DC bias signal to the third and fourth capacitors during the first clock cycle, wherein the first, second, third and fourth capacitors are each coupled to a respective input of the amplifier.
Claim 3
Dependent Claim
89 words
The method of claim 1 and further comprising: coupling the first and third capacitors to fifth and sixth capacitors during a second clock cycle, wherein the fifth and sixth capacitors are coupled between a first output of the amplifier and respective first and second inputs of the amplifier; and coupling the fourth and second capacitors to seventh and eighth capacitors during the second clock cycle, wherein the seventh and eighth capacitors are coupled between a second output of the amplifier and respective third and fourth inputs of the amplifier.
Claim 4
Dependent Claim
64 words
The method of claim 1 wherein the first and second DC bias signals are generated by the steps of: passing a first current through a first circuit operable to produce a known voltage in response to the first current; and passing a second current through a second circuit operable to produce a known voltage in response to current provided from said second current device.
Claim 5
Dependent Claim
101 words
The method of claim 1 and further comprising: coupling an offset signal from a first output of the amplifier to a first capacitor connected to a first input of the amplifier; coupling an offset signal from a first output of the amplifier to a second capacitor connected to a second input of the amplifier; coupling an offset signal from a second output of the amplifier to a third capacitor connected to a third input of the amplifier; and coupling an offset signal from a second output of the amplifier to a fourth capacitor connected to a fourth input of the amplifier.
Claim 6
Dependent Claim
32 words
The method of claim 4 wherein each of the offset signals are coupled to the respective capacitors during a second clock cycle which is non-overlapping with respect to the first clock cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-04 | 1996-02-03 | 1996-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-04 | 2000-02-03 | 2000-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-04 | 2004-02-03 | 2004-08-04 | $7700.00 | Window Closed / Lapsed |