Signal processor for personal computers

Claim 2

Signal processing means for connection between a parallel printer port of a personal computer and an external printer, comprising: a first data buffer, a signal receiving port for receiving an external signal for monitoring by the signal processing means, a signal converter connected to said signal receiving port and selectively connected to said first data buffer for producing data containing information about the external signal and for transferring said data into said first data buffer, including analog converter means for converting an analog external signal monitored at said signal receiving port to a first digital signal, printer control means for selectively interconnecting the parallel printer port of the personal computer to the input of an external printer, said printer control means selectively enabling one of at least two interconnect modes, including a transparent mode in which the parallel printer port of the personal computer is connected to the input of an external printer, enabling direct throughput of printer control instructions between the personal computer and the external printer, and a nontransparent mode in which the connection between the parallel printer port of the personal computer and the external printer is blocked, logic control means connected to said first data buffer and coupled to the personal computer through the parallel printer port, said logic control means being responsive to instructions from the personal computer for controlling the signal processing means including the printer control means, and an oscillator clock connected to said analog converter means and to said logic control means, in which said analog converter means converts the analog external signal to said first digital signal at intervals established by said oscillator clock, which intervals are determined by instructions supplied from the personal computer to said oscillator clock through said logic control means.

Claim 3

Signal processing means as in claim 1 in which said analog converter means is a voltage-to-frequency converter, including counter means connected to said voltage-to-frequency converter responsive to the output of said voltage-to-frequency converter for producing a count containing information about the analog signal monitored by said voltage-to-frequency converter for storage in said first data buffer.

Claim 4

Signal processing means as in claim 2 in which said voltage-to-frequency converter outputs up to an 16-bit pulse train as said first digital signal and said first data buffer is at least an 16-bit buffer.

Claim 5

Signal processing means as in claim 1 in which said analog converter means is a analog-to-digital converter.

Claim 6

A signal processor controlled by a personal computer for connection between the parallel printer port of a personal computer and the input of an external printer, the processor comprising: a computer interconnect port including a plurality of pins for interconnection with compatible pins on the parallel printer port of a personal computer, one or more signal input ports at which one or more signals monitored by the signal processor are received, a signal converter connected to one said signal input port, a first data buffer connected to said signal converter, a printer interconnect port for interconnection with an external printer, and an address selector connected to said computer interconnect port and controlled by a personal computer connected thereto, said address selector also being connected to and including predetermined address codes therein for accessing other selected components of the signal processor, including said signal converter, said first data buffer, and said printer interconnect port, whereby a computer connected to said computer interconnect port accesses selected components through the computer interconnect port to retrieve information and control the signal processor, wherein said signal converter converts a signal monitored at said one or more signal input ports, in accordance with instructions from a personal computer, and produces a first digital signal containing information about the monitored signal, said first data buffer receives and stores information contained in said first digital signal for access and retrieval by a personal computer through said address selector, and said address selector selectively enables one of at least two interconnect modes in response to instructions from a personal computer, including, a transparent mode in which said computer interconnect port is connected to said printer interconnect port for direct throughput of printer control instructions between a personal computer and an external printer, and a nontransparent mode in which the connection between the address selector and computer interconnect port is blocked.

Claim 7

A signal processor controlled by a personal computer for connection between the parallel printer port of a personal computer and the input of an external printer, the processor comprising: a computer interconnect port including a plurality of pins for interconnection with compatible pins on the parallel printer port of a personal computer, one or more signal input ports at which one or more signals monitored by the signal processor are received, a signal converter connected to one said signal input port, a first data buffer connected to said signal converter, a printer interconnect port for interconnection with an external printer, and an address selector connected to said computer interconnect port and controlled by a personal computer connected thereto, said address selector also being connected to and including predetermined address codes therein for accessing other selected components of the signal processor, including said signal converter, said first data buffer, and said printer interconnect port, whereby a computer connected to said computer interconnect port accesses selected components through the computer interconnect port to retrieve information and control the signal processor, wherein said signal converter converts a signal monitored at said one or more signal input ports, in accordance with instructions from a personal computer, and produces a first digital signal containing information about the monitored signal, said first data buffer receives and stores information contained in said first digital signal for access and retrieval by a personal computer through said address selector, and said address selector selectively enables one of at least two interconnect modes in response to instructions from a personal computer, including, a transparent mode in which said computer interconnect port is connected to said printer interconnect port for direct throughput of printer control instructions between a personal computer and an external printer, and a nontransparent mode in which the connection between the address selector and computer interconnect port is blocked.

Claim 8

A signal processor as in claim 5 in which said signal converter is an analog-to-digital converter connected to one said signal input port at which an analog signal is monitored, said analog-to-digital converter being addressable through said address selector by a personal computer connected to said computer at said computer interconnect port for controlling the analog-to-digital conversion interval based on instructions from a personal computer.

Claim 9

A signal processor as in claim 6 in which said analog-to-digital converter is a voltage-to-frequency converter, the signal processor further including an oscillator clock connected to said address selector, said address selector further including predetermined address codes therein for accessing said oscillating clock as one of the selected components accessible by a personal computer connected to said computer interconnect port, the oscillator clock being connected to said voltage-to-frequency converter, wherein said oscillator clock operates at a predetermined frequency and is programmable in response to instructions from a personal computer to establish a digitizing cycle duration, said oscillator clock periodically resetting said first data buffer at intervals based on the digitizing cycle duration, and including a counter connected to said voltage-to-frequency converter and said first data buffer, said counter periodically accumulating a count containing information about a signal monitored at said one signal input port for transfer to said first data buffer.

Claim 10

A signal processor as in claim 7 in which said voltage-to-frequency converter outputs up to a 16-bit pulse train as said first digital signal and said first data buffer is at least a 16-bit buffer.

Claim 11

A signal processor as in claim 5 including a status buffer connected to one or more said signal input ports at which one or more digital status signals are monitored, said status buffer also being connected to said address selector which further includes predetermined address codes therein for accessing said status buffer as one of the selected components accessible by a personal computer connected to said computer interconnect port, said status buffer receiving and storing digital status information received at said one or more status signal input ports, which information is accessible by a personal computer through said address selector.

Claim 12

A signal processor as in claim 9 in which information stored in said status buffer is retrievable through said address selector by a personal computer connected to said computer interconnect port in 4-bit data nibbles, said status buffer having a capacity greater than 4-bits and individual 4-bit nibbles being addressable by a personal computer through said address selector until the entire status buffer has been read.

Claim 13

A signal processor as in claim 5 in which said first data buffer has a capacity exceeding 4-bits and said first data buffer is addressable by a personal computer through said address selector and said computer interconnect port in 4-bit data nibbles, whereby the information in said first data buffer is retrievable by a personal computer through said address selector by selectively addressing 4-bit data nibbles in said data buffer until the entire buffer has been read.

Claim 14

A signal processor as in claim 5 in which one or more of said signal input ports is a frequency input port connected to said first data buffer for monitoring one or more frequency input signals, wherein said first data buffer receives and stores information about said one or more frequency input signals for access and retrieval by a personal computer through said address selector.

Claim 15

A signal processor as in claim 12, including multiplexer means connected to said first data buffer, to said address selector, to said signal converter and to said frequency input port, wherein said multiplexer means provides a selectable data path between a selected one of said signal converter and said frequency input port at one end of the data path and said first data buffer at the other end of the data path, and said address selector includes a predetermined address code for accessing said multiplexer means as one of the selected components of the signal processor to determine the data path selected by said multiplexer means based on instructions from a personal computer connected to said computer interconnect port.

Claim 16

A signal processor as in claim 5 including one or more control signal output ports and an output signal buffer connected to said one or more signal output ports and also connected to said address selector, said address selector including predetermined address codes therein for accessing said output buffer as one of the selected components of the signal processor accessible by a personal computer connected to said computer interconnect port, said output buffer storing one or more digital control signals based on instructions from a personal computer for output through said one or more signal output ports.

Claim 17

A signal processor controlled by a personal computer for connection to the parallel printer port of a personal computer, comprising: a computer interconnect port including a plurality of pins for interconnection with compatible pins on the parallel printer port of a personal computer, one or more signal input ports at which one or more signals monitored by the signal processor are received, a signal converter connected to one said signal input port, a first data buffer connected to said signal converter, and an address selector connected to said computer interconnect port and controlled by a personal computer connected thereto, said address selector also being connected to and including predetermined address codes therein for accessing other selected components of the signal processor, including said signal converter and said first data buffer, whereby a computer connected to said computer interconnect port accesses selected components through the computer interconnect port to retrieve information and control the signal processor, and wherein said signal processor converts a signal monitored at said one or more signal input ports, in accordance with instructions from a personal computer, and produces a first digital signal containing information about the monitored signal, and said first data buffer receives and stores information contained in said first digital signal for access and retrieval by a personal computer through said address selector.

Claim 18

A signal processor controlled by a personal computer for connection to the parallel printer port of a personal computer, comprising: a computer interconnect port including a plurality of pins for interconnection with compatible pins on the parallel printer port of a personal computer, one or more signal input ports at which one or more signals monitored by the signal processor are received, a signal converter connected to one said signal input port, a first data buffer connected to said signal converter, and an address selector connected to said computer interconnect port and controlled by a personal computer connected thereto, said address selector also being connected to and including predetermined address codes therein for accessing other selected components of the signal processor, including said signal converter and said first data buffer, whereby a computer connected to said computer interconnect port accesses selected components through the computer interconnect port to retrieve information and control the signal processor, and wherein said signal processor converts a signal monitored at said one or more signal input ports, in accordance with instructions from a personal computer, and produces a first digital signal containing information about the monitored signal, and said first data buffer receives and stores information contained in said first digital signal for access and retrieval by a personal computer through said address selector.

Claim 19

A signal processor as in claim 15 in which said signal converter is an analog-to-digital converter connected to one said signal input port at which an analog signal is monitored, said analog-to-digital converter being addressable through said address selector by a personal computer connected to said computer at said computer interconnect port for controlling the analog-to-digital conversion interval based on instructions from a personal computer.

Claim 20

A signal processor as in claim 16 in which said analog-to-digital converter is a voltage-to-frequency converter, the signal processor further including an oscillator clock connected to said address selector, the address selector further including predetermined address codes therein for accessing said oscillating clock as one of the selected components accessible by a personal computer connected to said computer interconnect port, said oscillator clock being connected to said voltage-to-frequency converter, wherein said oscillator clock operates at a predetermined frequency and is programmable in response to instructions from a personal computer to establish a digitizing cycle duration, said oscillator clock periodically resetting said first data buffer at intervals based on the digitizing cycle duration, and including a counter connected to said voltage-to-frequency converter and said first data buffer, said periodically accumulating a count containing information about a signal monitored at said one signal input port for transfer to said first data buffer.

Claim 21

A signal processor as in claim 17 in which said voltage-to-frequency converter outputs up to a 16-bit pulse train as said first digital signal and said first data buffer is at least a 16-bit buffer.

Claim 22

A signal processor as in claim 15 including a status buffer connected to one or more said signal input ports at which one or more digital status signals are monitored, said status buffer also being connected to said address selector which further includes predetermined address codes therein for accessing said status buffer as one of the selected components accessible by a personal computer connected to said computer interconnect port, said status buffer receiving and storing digital status information received at said one or more status signal input ports, which information is accessible by a personal computer through said address selector.

Claim 23

A signal processor as in claim 19 in which information stored in said status buffer is retrievable through said address selector by a personal computer connected to said computer interconnect port in 4-bit data nibbles, said status buffer having a capacity greater than 4-bits and individual 4-bit nibbles being addressable by a personal computer through said address selector until the entire status buffer has been read.

Claim 24

A signal processor as in claim 15 in which said first data buffer has a capacity exceeding 4-bits and said first data buffer is addressable by a personal computer through said address selector and said computer interconnect port in 4-bit data nibbles, whereby the information in said first data buffer is retrievable by a personal computer through said address selector by selectively addressing 4-bit data nibbles in said data buffer until the entire buffer has been read.

Claim 25

A signal processor as in claim 15 in which one or more of said signal input ports is a frequency input port connected to said first data buffer for monitoring one or more frequency input signals, wherein said first data buffer receives and stores information about said one or more frequency input signals for access and retrieval by a personal computer through said address selector.

Claim 26

A signal processor as in claim 22, including multiplexer means connected to said first data buffer, to said address selector, to said signal converter and to said frequency input port, wherein said multiplexer means provides a selectable data path between a selected one of said signal converter and said frequency input port at one end of the data path and said first data buffer at the other end of the data path, and said address selector includes a predetermined address code for accessing said multiplexer means as one of the selected components of the signal processor to determine the data path selected by said multiplexer means based on instructions from a personal computer connected to said computer interconnect port.

Claim 27

A signal processor as in claim 15 including one or more control signal output ports and an output signal buffer connected to said one or more signal output ports and also connected to said address selector, said address selector including predetermined address codes therein for accessing said output buffer as one of the selected components of the signal processor accessible by a personal computer connected to said computer interconnect port, said output buffer storing one or more digital control signals based on instructions from a personal computer for output through said one or more signal output ports.