US5130772A
Expired / Lapsed
US
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Thin film transistor with a thin layer of silicon nitride
Assignee: Samsung SDI Co Ltd
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Filing: 1991-04-23
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Granted: 1992-07-14
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Expires: 2011-04-23
Abstract
Abstract There is disclosed a thin film transistor, wherein the lengthwise direction of the source is made parallel to that of the gate, and an insulating layer is continuously deposited between double gates and the semiconductor layer to obstruct the pin holes generated during first deposition. Further, between overlapping semiconductor layers there is interposed an insulating layer to prevent short circuit of the electrodes due to the pin holes in the semiconductor layers.
Inventors
- 👤 Kwangsoo Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:34
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/6757
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
110 words
A thin film transistor comprising a capacitor electrode formed on a glass substrate, an insulating layer deposited over said capacitor electrode, an indium tin oxide (ITO) electrode formed on said insulating layer, a gate formed on said ITO electrode, first and second gate insulating layers of silicon oxide (SiO 2 ) deposited on said gate, first and second semiconductor layers of amorphous silicon deposited on said insulating layers, with an insulating layer of amorphous silicon nitride sufficiently thin to enable tunneling and interposed between said first and second semiconductor layers, an ohmic layer deposited on said second semiconductor layer, and a source and a drain deposited on said ohmic layer.
Claim 2
Dependent Claim
110 words
A thin film transistor comprising a capacitor electrode formed on a glass substrate, an insulating layer deposited over said capacitor electrode, an indium tin oxide (ITO) electrode formed on said insulating layer, a gate formed on said ITO electrode, first and second gate insulating layers of silicon oxide (SiO 2 ) deposited on said gate, first and second semiconductor layers of amorphous silicon deposited on said insulating layers, with an insulating layer of amorphous silicon nitride sufficiently thin to enable tunneling and interposed between said first and second semiconductor layers, an ohmic layer deposited on said second semiconductor layer, and a source and a drain deposited on said ohmic layer.
Claim 3
Dependent Claim
29 words
A thin film transistor as in claim 1 wherein the lengthwise directions of the drain, semiconductor layers, and gate are in parallel with the lengthwise direction of the source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-14 | 1996-01-13 | 1996-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-14 | 2000-01-13 | 2000-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-14 | 2004-01-13 | 2004-07-14 | $7700.00 | Window Closed / Lapsed |