US5128998A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Head or arbitrary bit pulse generating circuit and sampling pulse generating circuit in a pseudo noise code generator
Assignee: Faurecia Clarion Electronics Co Ltd
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Filing: 1990-09-21
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Granted: 1992-07-07
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Expires: 2010-09-21
Abstract
Abstract A pseudo noise code generator is disclosed, in which the shift register value of the pseudo noise code generator corresponding to the generation timing of a bit pulse or a sampling pulse is latched and the output of the latch is compared with the shift register value of the generator, the bit pulse or the sampling pulse being obtained, when they are in accordance with each other.
Inventors
- 👤 Takao Kurihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:47
CPC Classifications
H; H04; H04J; H04J13/00; H04J13/0007; H04J13/0022; H03; H03K; H03K3/00; H03K3/84; H04J13/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
133 words
A circuit comprising: a pseudonoise code generator having a shift register which outputs a sequence of values; and a bit pulse generating circuit which includes: a latch circuit which latches a shift register value periodically appearing in said sequence of values output by said shift register of said pseudonoise code generator at respective points in time when a bit pulse is to be generated; and a comparing circuit which is coupled to said latch circuit and to said shift register, which compares each value of said sequence of values output by said shift register of said pseudonoise code generator with said shift register value in said latch circuit and which outputs a bit pulse only when the value currently output by said shift register equals said shift register value in said latch circuit.
Claim 2
Dependent Claim
133 words
A circuit comprising: a pseudonoise code generator having a shift register which outputs a sequence of values; and a bit pulse generating circuit which includes: a latch circuit which latches a shift register value periodically appearing in said sequence of values output by said shift register of said pseudonoise code generator at respective points in time when a bit pulse is to be generated; and a comparing circuit which is coupled to said latch circuit and to said shift register, which compares each value of said sequence of values output by said shift register of said pseudonoise code generator with said shift register value in said latch circuit and which outputs a bit pulse only when the value currently output by said shift register equals said shift register value in said latch circuit.
Claim 3
Dependent Claim
95 words
A circuit according to claim 1, wherein said shift register has a plurality of outputs and said latch circuit has a plurality of outputs, wherein said comparing circuit includes a plurality of exclusive NOR gates each having an output and having two inputs respectively coupled to a respective said output of said shift register and a respective said output of said latch circuit, and an AND gate having an output which carries said bit pulse and having a plurality of inputs each coupled to the output of a respective one of said exclusive NOR gates.
Claim 4
Dependent Claim
133 words
A circuit comprising: a pseudonoise code generator having a shift register which outputs a sequence of values; and a sampling pulse generating circuit which includes: a latch circuit which latches a shift register value periodically appearing in said sequence of values output by said shift register of said pseudonoise code generator at respective points in time when a sampling pulse is to be generated; and a comparing circuit which is coupled to said latch circuit and to said shift register, which compares each value of said sequence of values output by said shift register of said pseudonoise code generator with said shift register value in said latch circuit and which outputs a sampling pulse only when the value currently output by said shift register equals said shift register value in said latch circuit.
Claim 5
Dependent Claim
133 words
A circuit comprising: a pseudonoise code generator having a shift register which outputs a sequence of values; and a sampling pulse generating circuit which includes: a latch circuit which latches a shift register value periodically appearing in said sequence of values output by said shift register of said pseudonoise code generator at respective points in time when a sampling pulse is to be generated; and a comparing circuit which is coupled to said latch circuit and to said shift register, which compares each value of said sequence of values output by said shift register of said pseudonoise code generator with said shift register value in said latch circuit and which outputs a sampling pulse only when the value currently output by said shift register equals said shift register value in said latch circuit.
Claim 6
Dependent Claim
128 words
A circuit according to claim 3, wherein said latch circuit includes a first latch which latches said shift register value and a second latch which latches a further value periodically appearing in said sequence and different from said shift register value in said first latch, and wherein said comparing circuit includes a first comparing circuit which is coupled to said shift register and said first latch and outputs said sampling pulse, and a second comparing circuit which is coupled to said second latch and to said shift register, which compares each value of said sequence of values with said further value in said second latch, and which outputs a further pulse when the value currently produced by said shift register equals said further value in said second latch.
Claim 7
Dependent Claim
95 words
A circuit according to claim 3, wherein said shift register has a plurality of outputs and said latch circuit has a plurality of outputs, wherein said comparing circuit includes a plurality of exclusive NOR gates each having an output and having two inputs respectively coupled to a respective said output of said shift register and a respective said output of said latch circuit, and an AND gate having an output which carriers said sampling pulse and having a plurality of inputs each coupled to the output of a respective one of said exclusive NOR gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |