US5128958A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital time error signal generator
Assignee: Unisys Corp
•
Filing: 1990-07-26
•
Granted: 1992-07-07
•
Expires: 2010-07-26
Abstract
Abstract A time error signal generator of the type employed in symbol time tracking loops is provided with a pre-accumulate and scale circuit for receiving an input data stream which is applied to a digital early sample-late sample circuit for generation an error signal indicative of a time magnitude difference between the analog transition time of the data and the chip strobe time multiplied by the sign of the data. The output of the early sample-late sample circuit is applied to a second accumulate and scale circuit for generating an accumulated error signal which is applied to an inverter. The inverter is provided with a decision directed tracking input indicative of the sign of the data sample and is employed to invert the accumulated error signal when the sign of the analog data is negative. The output of the inverter provides a digital time error tracking signal which is adapted to be coupled to a clock generation circuit or clock synthesizer for generating the tracking loop system clock as well as other strobe timing signals.
Inventors
- 👤 Samuel C. Kingston
- 👤 Steven T. Barham
- 👤 Harold L. Simonsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:21
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/7073; H04B1/7085
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
181 words
A digital time error signal generator circuit of the type employed to synchronize input data and chip strobe time of a communications receiver, comprising: input data means, digital early sample-late sample circuit means coupled to said input data means to provide a stream of input data for generating an output error signal indicative of a time magnitude difference between transition time of the input data and chip strobe time of the generator circuit multiplied by the sign of the input data, accumulate and scale means coupled to an output of said digital early sample-late sample circuit means for generating an accumulated error signal, inverter means having input means coupled to said accumulated error signal, and decision directed sign control input means coupled to said inverter means for indicating the sign of the input data and inverting said accumulated error signal sign when the sign of the input data is negative, said inverter means having an output port which provides a digital time error tracking signal used for synchronizing the occurrence of said chip strobe time with said input data transition time.
Claim 2
Dependent Claim
181 words
A digital time error signal generator circuit of the type employed to synchronize input data and chip strobe time of a communications receiver, comprising: input data means, digital early sample-late sample circuit means coupled to said input data means to provide a stream of input data for generating an output error signal indicative of a time magnitude difference between transition time of the input data and chip strobe time of the generator circuit multiplied by the sign of the input data, accumulate and scale means coupled to an output of said digital early sample-late sample circuit means for generating an accumulated error signal, inverter means having input means coupled to said accumulated error signal, and decision directed sign control input means coupled to said inverter means for indicating the sign of the input data and inverting said accumulated error signal sign when the sign of the input data is negative, said inverter means having an output port which provides a digital time error tracking signal used for synchronizing the occurrence of said chip strobe time with said input data transition time.
Claim 3
Dependent Claim
36 words
A digital time error signal generator as set forth in claim 1 wherein said digital early sample-late sample circuit means comprises a first pre-accumulate and scale circuit connected in series in said stream of input data.
Claim 4
Dependent Claim
29 words
A digital time error signal generator as set forth in claim 2 which further comprises a loop filter coupled to said inverter for producing a sample rate frequency command.
Claim 5
Dependent Claim
38 words
A digital time error signal generator as set forth in claim 3 wherein said sample rate frequency command provided as an output from said loop filter is applied to a clock synthesizer for producing a sampling clock signal.
Claim 6
Dependent Claim
40 words
A digital time error signal generator as set forth in claim 4 is an on chip I.C. circuit and wherein the output of said inverter means is adapted to be connected to off chip and on chip clock generation means.
Claim 7
Dependent Claim
22 words
A digital time error signal generator as set forth in claim 3 wherein said loop filter is a second order loop filter.
Claim 8
Dependent Claim
40 words
A digital time error signal generator as set forth in claim 1 which further includes despreader means connected in series between the output error signal output of said early sample-late sample circuit connected means and said accumulate and scale means.
Claim 9
Dependent Claim
79 words
A digital time error signal generator as set forth in claim 1 wherein said time error signal generator comprises two data channels each having one said early sample-late sample circuit means and one said accumulate and scale means for generating a said accumulated error signal, each said accumulate error signal from said channels being applied to a multiplexor for selecting one of said two data channels and having an output port connected to an input of said inverter means.
Claim 10
Dependent Claim
40 words
A digital time error signal generator as set forth in claim 1 is an on chip I.C. circuit and wherein the output of said inverter means is adapted to be connected to off chip and on chip clock generation means.
Claim 11
Dependent Claim
24 words
A digital time error signal generator as set forth in claim 1 wherein said decision directed sign control input means comprises a command generator.
References Cited (Backward Citations)
US4166979A
Cited
US4301537A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |