US5128929A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time division switching system capable of broad band communications service
Assignee: NEC Corp
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Filing: 1989-11-14
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Granted: 1992-07-07
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Expires: 2009-11-14
Abstract
Abstract Sometimes digital data become out of order as it passes through a time division switching system. This invention restores the proper order by transmitting sequence information with the digital data. At the receive end, the data is assembled in its proper and original order in buffer storage means responsive to the sequence information.
Inventors
- 👤 Tsuneo Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:36
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/06
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
319 words
A time division switching system for switching K-bit (K is a positive integer) transmit data and L-bit (L is a positive integer which is equal to or greater than 2) control data, the switching system comprising: transmitting means on a sending side for transmitting sequence information when K-bit×P (P is a positive integer, and 2≦P≦0) multi-element data constituting a sequence of data occupies P channels in a single frame are to be switched, said sequence information correcting the sequence of said multi-element data as part of said control data in synchronism with said multi-element data, all of said transmit data being sent to a time division multiplexed input highway having 0 channels (0 is a positive integer which is equal to or greater than 2) of time division switching equipment; and the switching system having a receiving side, R (R is a positive integer which is equal to or greater than 3) numbers of buffer memories on said receiving side for receiving and storing said multi-element data received from a time division multiplexed output highway having 0 channels of said switching equipment, accumulating means for sequentially accumulating said multi-element data in said buffer memories depending on said sequence information which has been received, and sequence correcting means for correcting and outputting the sequence of said multi-element data stored in said buffer memories when all of said multi=element data sent within the same frame from the sending side have been accumulated in one of said buffer memories on said receiving side; said sequence information being set in correspondence to each of said buffer memories, said multi-element data being accumulated in the buffer memory of said accumulating means as indicated by said sequence information which is received together with said multi-element data; and said transmitting means includes an R-nary counter which counts up in response to every transmit frame, said sequence information comprising data encoded into the output of the counter.
Claim 2
Dependent Claim
319 words
A time division switching system for switching K-bit (K is a positive integer) transmit data and L-bit (L is a positive integer which is equal to or greater than 2) control data, the switching system comprising: transmitting means on a sending side for transmitting sequence information when K-bit×P (P is a positive integer, and 2≦P≦0) multi-element data constituting a sequence of data occupies P channels in a single frame are to be switched, said sequence information correcting the sequence of said multi-element data as part of said control data in synchronism with said multi-element data, all of said transmit data being sent to a time division multiplexed input highway having 0 channels (0 is a positive integer which is equal to or greater than 2) of time division switching equipment; and the switching system having a receiving side, R (R is a positive integer which is equal to or greater than 3) numbers of buffer memories on said receiving side for receiving and storing said multi-element data received from a time division multiplexed output highway having 0 channels of said switching equipment, accumulating means for sequentially accumulating said multi-element data in said buffer memories depending on said sequence information which has been received, and sequence correcting means for correcting and outputting the sequence of said multi-element data stored in said buffer memories when all of said multi=element data sent within the same frame from the sending side have been accumulated in one of said buffer memories on said receiving side; said sequence information being set in correspondence to each of said buffer memories, said multi-element data being accumulated in the buffer memory of said accumulating means as indicated by said sequence information which is received together with said multi-element data; and said transmitting means includes an R-nary counter which counts up in response to every transmit frame, said sequence information comprising data encoded into the output of the counter.
Claim 3
Dependent Claim
29 words
A time division switching system as claimed in claim 1, wherein said accumulating means rotationally uses said R buffer memories in accumulating said multi-element data as they are received.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |