US5126845A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipeline bus having registers and selector for real-time video signal processing
Assignee: IMAGICA Lab Inc
•
Filing: 1990-07-23
•
Granted: 1992-06-30
•
Expires: 2010-07-23
Abstract
Abstract A pipeline bus having a plurality of slots in a backplane for receiving functional modules. A bus line is connected between the slots. A register and a selector are provided between each two adjacent slots. An image signal and a sync signal are transmitted from upper to lower slots in synchronism with the clock signal. The selectors output a signal either from the register or from the associated functional module to the register which is downstream.
Inventors
- 👤 Shinichi Yamashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:53
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
94 words
A video signal pipeline bus, comprising: a backplane having a plurality of slots for receiving functional modules; a bus line mounted on said backplane and interconnecting said slots; a plurality of registers and a plurality of selectors connected to said bus line and mounted on said backplane, with one selector and one register being connected between adjacent slots on the bus line, each of said selectors receiving one input from the associated functional module and one input from the immediately preceding register and producing an output which is the input to the next register.
Claim 2
Dependent Claim
94 words
A video signal pipeline bus, comprising: a backplane having a plurality of slots for receiving functional modules; a bus line mounted on said backplane and interconnecting said slots; a plurality of registers and a plurality of selectors connected to said bus line and mounted on said backplane, with one selector and one register being connected between adjacent slots on the bus line, each of said selectors receiving one input from the associated functional module and one input from the immediately preceding register and producing an output which is the input to the next register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |