US5124849A
Expired / Lapsed
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Data storage media certification process
Assignee: Swan Instruments Inc
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Filing: 1990-06-01
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Granted: 1992-06-23
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Expires: 2010-06-01
Abstract
Abstract A method for detecting aberrations in a digital data storage medium, such as a magnetic media disk. In a media certifier, a series of signal pulses is produced by reading data previously written to a medium is examined for differential variations between each signal pulse and at least one other of those signal pulses in the local area of the medium. A signal indicative of such differential variations is isolated by means of a CYCOMP circuit (54) and/or a band reject circuit (140). The CYCOMP circuit (54) works by delaying a previously produced signal for comparison to the cycle of the signal presently being produced and then producing a differential signal representing any instantaneous difference between the two signals. The band reject circuit (140) works by eliminating any frequency content that would be present in a series of normal signals and thus isolating any asynchronous signal that is indicative of an aberration. Both the CYCOMP circuit (54) and the band reject circuit (140) use comparators (114), (118) and (152) to determine if any detected differential signal rises above a preset error indication threshold.
Inventors
- 👤 Sung P. Chur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:23
CPC Classifications
G; G11; G11B; G11B23/00; G11B20/00; G11B20/10; G11B20/18; G11B20/1816; G11B20/182; G11B33/00; G11B33/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
147 words
A method for detecting faults in a digital storage medium, in steps comprising: a) writing a series of bits of digital information to the medium; b) transforming the series of bits of digital information into a plurality of read back signal cycles wherein each of said cycles is a product of one of the series of bits of digital information previously written; c) extracting from said cycles an error signal comprising any instantaneous deviation between a portion of any of said cycles and a corresponding expected normal instant signal level; and d) comparing said error signal to a reference value and registering an error indication when said error signal exceeds said reference value, wherein said error signal is extracted from each of said cycles by continuously comparing each of said cycles to a comparison signal, said comparison signal comprising a phase inverted version of a previous cycle.
Claim 2
Independent Claim
147 words
A method for detecting faults in a digital storage medium, in steps comprising: a) writing a series of bits of digital information to the medium; b) transforming the series of bits of digital information into a plurality of read back signal cycles wherein each of said cycles is a product of one of the series of bits of digital information previously written; c) extracting from said cycles an error signal comprising any instantaneous deviation between a portion of any of said cycles and a corresponding expected normal instant signal level; and d) comparing said error signal to a reference value and registering an error indication when said error signal exceeds said reference value, wherein said error signal is extracted from each of said cycles by continuously comparing each of said cycles to a comparison signal, said comparison signal comprising a phase inverted version of a previous cycle.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein: a non-zero value of said error signal is produced by any amplitude deviation between any of said cycles and said comparison signal.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein: a non-zero value of said error signal is produced by any phase deviation between any of said cycles and said comparison signal.
Claim 5
Dependent Claim
56 words
The method of claim 1, wherein: said error signal is extracted from said cycles by removing from said cycles a basic component of said cycles, said basic component comprising a fundamental frequency of said cycle, and; said basic component which is removed from said cycles further includes a plurality of lower harmonics of said fundamental frequency.
Claim 6
Dependent Claim
174 words
In a process for detecting errors present in a digital storage medium read back signal, including the steps of writing data to the medium, reading back the data just written in order to produce the read back signal, and examining the read back signal by various conventional means to detect errors, the improvement comprising: further examining each of a plurality of cycles of the read back signal for an instantaneous high voltage level, said instantaneous high voltage level being any instantaneous voltage level which is higher than an expected instantaneous voltage level, and; examining each of the plurality of cycles of the read back signal for an instantaneous low voltage level, said instantaneous low voltage level being any instantaneous voltage level which is lower than said expected instantaneous voltage level, wherein; said expected instantaneous voltage level is zero volts, and said instantaneous high voltage level and said instantaneous low voltage level include any signal present after removing a fundamental frequency and any of a plurality of lower harmonic frequencies from the read back signal.
Claim 7
Dependent Claim
174 words
In a process for detecting errors present in a digital storage medium read back signal, including the steps of writing data to the medium, reading back the data just written in order to produce the read back signal, and examining the read back signal by various conventional means to detect errors, the improvement comprising: further examining each of a plurality of cycles of the read back signal for an instantaneous high voltage level, said instantaneous high voltage level being any instantaneous voltage level which is higher than an expected instantaneous voltage level, and; examining each of the plurality of cycles of the read back signal for an instantaneous low voltage level, said instantaneous low voltage level being any instantaneous voltage level which is lower than said expected instantaneous voltage level, wherein; said expected instantaneous voltage level is zero volts, and said instantaneous high voltage level and said instantaneous low voltage level include any signal present after removing a fundamental frequency and any of a plurality of lower harmonic frequencies from the read back signal.
Claim 8
Independent Claim
170 words
An apparatus for detecting signal cycle aberrations in a digital storage medium read back signal, including: a delay means for delaying the read back signal to produce a delayed read back signal, said delayed read back signal being delayed by at least one period of the read back signal; an inverting means for inverting said delayed read back signal thus producing an inverted delayed read back signal; a summing means for summing the read back signal with said inverted delayed read back signal such that any instantaneous difference between the read back signal and said delayed read back signal produces an aberration signal; a peak following means for establish a direct current voltage level representing a prevailing value of peak values of the read back signal; a error detect threshold selection means for establishing an error detect threshold as a percentage of said direct current voltage level; and an error detection means for producing an error signal when an absolute value of said aberration signal exceeds said error detect threshold.
Claim 9
Independent Claim
170 words
An apparatus for detecting signal cycle aberrations in a digital storage medium read back signal, including: a delay means for delaying the read back signal to produce a delayed read back signal, said delayed read back signal being delayed by at least one period of the read back signal; an inverting means for inverting said delayed read back signal thus producing an inverted delayed read back signal; a summing means for summing the read back signal with said inverted delayed read back signal such that any instantaneous difference between the read back signal and said delayed read back signal produces an aberration signal; a peak following means for establish a direct current voltage level representing a prevailing value of peak values of the read back signal; a error detect threshold selection means for establishing an error detect threshold as a percentage of said direct current voltage level; and an error detection means for producing an error signal when an absolute value of said aberration signal exceeds said error detect threshold.
Claim 10
Dependent Claim
78 words
The apparatus of claim 6, and further including: a filtering means for filtering a fundamental frequency from the read back signal thus producing a filtered read back signal; an auxiliary error detect threshold selection means for establishing an auxiliary error detect threshold as a percentage of said direct current voltage level; and an auxiliary error detection means for producing an error signal when an absolute value of said filtered read back signal exceeds said auxiliary error detect threshold.
Claim 11
Dependent Claim
77 words
The apparatus of claim 6, wherein: said delayed read back signal is delayed by an amount such that each of a plurality of cycles of the read back signal is summed with an inversion of a next previous of said cycles, said next previous of said cycles having the characteristic of being the last of said cycles to be examined such each of said cycles sequentially becomes the next previous of said cycles with each new repetition.
Claim 12
Dependent Claim
78 words
The apparatus of claim 8, and further including: a loss compensation means for summing a portion of the read back signal into said delayed read back signal, said portion being just sufficient to compensate for losses occurring in said delay means such that, for those portions of the read back signal wherein all sequential of said cycles of the read back signal are identical, the read back signal and said delayed read back signal are of equal magnitude.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |