US5124670A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency synthesizers with fractional division
Assignee: Plessey Semiconductors Ltd
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Filing: 1990-04-02
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Granted: 1992-06-23
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Expires: 2010-04-02
Abstract
Abstract A fractional-N synthesizer including a phase locked loop comprising: a voltage controlled oscillator (4) providing a loop output signal, the output signal being coupled via an N variable divider (6) to a first input of a phase or frequency detector (8); a reference frequency source coupled to a second input of the phase or frequency detector (8), the detector providing at an output a control signal, in dependence upon a comparision between the signals applied to the first and second inputs, for application to a control input of the voltage controlled oscillator (4); and means for setting the division ratio (N) of the variable divider (6) in response to a frequency data word, including interpolator means (50) for periodically varying at least the LSB of the frequency data word, the interpolator means (50) comprising an input for receiving said LSB, a combiner means (70, 80) for comparing the LSB with a feedback signal, and a quantizer circuit (72, 84) and a filter circuit (74, 82) providing a predetermined delay or integration function, such circuits being coupled to said combiner means (70, 80) for providing said feedback signal and a ratio setting signal to the variable divider (6).
Inventors
- 👤 Rodney J. Lawton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:55
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H03L7/1976
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
217 words
A fractional-N synthesizer including a phase locked loop comprising: a voltage controlled oscillator providing a loop output signal, the output signal being coupled by way of a divide by N variable divider to a first input of a phase detector; a reference frequency source coupled to a second input of the phase detector, the detector providing at an output a control signal, in dependence upon a comparison between the signals applied to the first and second inputs, for application to a control input of the voltage controlled oscillator; and means for setting the division ratio N of the variable divider, in response to a frequency data word, including interpolator means for periodically varying at least the least significant bit of the frequency data word, the interpolator means comprising an input for receiving an input data word, a combiner means for combining the input data word with a feedback signal, a quantiser circuit, means for connecting an output of said combining means to said quantiser circuit, a filter circuit providing a predetermined integration function, means connecting said filter circuit to receive a quantisation error signal from the quantiser, and means connecting the output of the filter circuit as the feedback signal to said combiner means, said frequency data word being derived from an output of the quantiser circuit.
Claim 2
Dependent Claim
217 words
A fractional-N synthesizer including a phase locked loop comprising: a voltage controlled oscillator providing a loop output signal, the output signal being coupled by way of a divide by N variable divider to a first input of a phase detector; a reference frequency source coupled to a second input of the phase detector, the detector providing at an output a control signal, in dependence upon a comparison between the signals applied to the first and second inputs, for application to a control input of the voltage controlled oscillator; and means for setting the division ratio N of the variable divider, in response to a frequency data word, including interpolator means for periodically varying at least the least significant bit of the frequency data word, the interpolator means comprising an input for receiving an input data word, a combiner means for combining the input data word with a feedback signal, a quantiser circuit, means for connecting an output of said combining means to said quantiser circuit, a filter circuit providing a predetermined integration function, means connecting said filter circuit to receive a quantisation error signal from the quantiser, and means connecting the output of the filter circuit as the feedback signal to said combiner means, said frequency data word being derived from an output of the quantiser circuit.
Claim 3
Dependent Claim
37 words
A synthesizer as claimed in claim 1 comprising means to receive signals from the input and output of the quantiser circuit and to generate said quantisation error signal from the difference between said input and output signals.
Claim 4
Dependent Claim
43 words
A synthesiser as claimed in claim 1 wherein the interpolator is operative to receive a K bit word and produce an M bit word for application to a control input of the variable divider, where the value of M periodically varies and K>M.
Claim 5
Dependent Claim
15 words
A synthesiser as claimed in claim 1 wherein the quantiser circuit is an M-bit quantiser.
Claim 6
Dependent Claim
29 words
A synthesiser as claimed in claim 1 wherein the interpolator arrangement comprises a plurality of coders connected in cascade; and having their outputs coupled to provide a common output.
Claim 7
Dependent Claim
24 words
A synthesiser circuit as claimed in claim 5 wherein the order of the coder is determined by the number of coders connected in cascade.
Claim 8
Dependent Claim
24 words
A synthesiser as claimed in claim 1 wherein the interpolator arrangement comprises an n th order coder, where n=1, 2, 3 or higher integer.
Claim 9
Dependent Claim
24 words
A synthesizer circuit as claimed in claim 7 wherein the order of the coder is determined by the number of coders connected in cascade.
Claim 10
Dependent Claim
25 words
A synthesiser circuit as claimed in claim 1 wherein the order of the coder is determined by the transfer function H(z) of the filter circuit.
Claim 11
Dependent Claim
26 words
A synthesiser circuit as claimed in claim 1 wherein the ratio setting signal is applied to a memory store prior to application to said variable divider
References Cited (Backward Citations)
US4758802A
Cited
US4800342A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |