Memory circuit having an erasable programmable memory

Claim 2

An integrated memory circuit, comprising an erasable programmable memory, a generator for generating a programming voltage for the memory, which generator comprises a charge pump, and at least one of a voltage controller coupled to said generator for limiting the programming voltage and an edge controller coupled to said generator for limiting an increase of the programming voltage per unit of time, wherein the at least one controller generates a control signal for switching the charge pump on or off as a function of at least one of the programming voltage and a variation per unit of time of the programming voltage.

Claim 3

An integrated memory circuit as claimed in claim 1, characterized in that the at least one controller comprises, connected between a first and a second power supply terminal, a series arrangement of a first and a second current source, at least one of the current sources being controllable on a relevant control terminal via a detector for the programming voltage, a control signal being generated on a junction point between the current sources.

Claim 4

An integrated memory circuit as claimed in claim 2, comprising both a voltage controller and an edge controller, characterized in that the respective junction points between the current sources in the respective series connections are connected to respective gate inputs of a logic gate which switches the charge pump.

Claim 5

An integrated memory circuit as claimed in claim 2 or 3, in which the generator comprises the voltage controller, characterized in that one of said current sources in the voltage controller is controllable by the relevant detector whose detector output is connected to the relevant control terminal, which detector comprises a cascode connection with a third current source which is connected between the first power supply terminal and the detector output and a Zener diode which is connected between the detector output and a point carrying the programming voltage.

Claim 6

An integrated memory circuit as claimed in claim 4, characterized in that between the detector output and the Zener diode there is connected a current channel of an amplifier field-effect transistor, a control electrode of which is connected to the first power supply terminal, a substrate terminal thereof receiving the programming voltage.

Claim 7

An integrated memory circuit as claimed in claim 4, characterized in that the Zener diode comprises a drain diode of a field-effect transistor.

Claim 8

A memory circuit as claimed in claim 6, characterized in that the field-effect transistor is constructed so as to have an annular control electrode.

Claim 9

An integrated memory circuit as claimed in claim 2, in which the generator comprises the edge controller, characterized in that one of said current sources in the edge controller is controllable by the relevant detector, a detector output of which is connected to the relevant control terminal, which detector comprises a further cascode connection with a fourth current source which is connected between the first power supply terminal and the detector output and with a capacitance which is connected between the detector output and a point carrying the programming voltage.

Claim 10

An integrated memory circuit as claimed in claim 8, characterized in that between the detector output of the further cascode connection and the capacitance there is connected a current channel of a charging field-effect transistor, a control electrode of which is connected to the first power supply terminal and a substrate terminal of which is connected to the second power supply terminal.

Claim 11

An integrated memory circuit as claimed in claim 9, characterized in that a diode is connected at an anode side to a junction point between the capacitance and the charging transistor and at a cathode side to one of the power supply terminals.

Claim 12

An integrated memory circuit as claimed in claim 2, characterized in that in the at least one controller the first current source between the first power supply terminal and the junction point comprises a current channel of a first field-effect transistor of the first conductivity type, a control electrode of which forms the first control terminal, the second current source between the junction point and the second power supply terminal comprising a current channel of a second field-effect transistor of the second conductivity type, which second field-effect transistor constitutes a current mirror in conjunction with a reference field-effect transistor, the reference field-effect transistor conducting a reference current.

Claim 13

An integrated memory circuit as claimed in claim 4, characterized in that the current source in said cascode connection comprises a third field-effect transistor of a first conductivity type having a current channel connected between the first power supply terminal and the output of said cascode connection, which third field-effect transistor forms a current mirror in conjunction with a further reference transistor, which further reference transistor conducts a further reference current.