Reducing dark current in charge coupled devices

Claim 1

A method of reducing dark current during the operation of a two phase buried channel CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 and the second pixel gate to a phase line O 2 , the method comprising the step of: simultaneously applying appropriate voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel.

Claim 2

A method of reducing dark current during the operation of a two phase buried channel CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 and the second pixel gate to a phase line O 2 , the method comprising the step of: simultaneously applying appropriate voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel.

Claim 3

A method of reducing dark current during the operation of a two phase, buried channel CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 and the second pixel gate being connected to a phase line O 2 , each CCD buried channel gate having transfer and storage regions sequentially formed under each gate, the method comprising the step of: simultaneously applying voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel with the difference in channel potentials of the transfer regions so chosen that a given pixel signal is not mixed with signals contained in adjacent pixels.

Claim 4

A method of reducing dark current during the operation of a two phase, buried channel CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 and the second pixel gate being connected to a phase line O 2 , each CCD buried channel gate having transfer and storage regions sequentially formed under each gate, the method comprising the step of: simultaneously applying voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel with the difference in channel potentials of the transfer regions so chosen that a given pixel signal is not mixed with signals contained in adjacent pixels.

Claim 5

A method of reducing dark current during the operation of a true two phase, buried channel CCD having a p-type substrate and an n-buried channel, with such CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 , and the second pixel gate to a phase line O 2 , each CCD buried channel gate having transfer and storage regions sequentially formed under each gate, the method comprising the step of: simultaneously applying voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel with the difference in channel potentials of the transfer regions so chosen that a given pixel signal is not mixed with signals contained in adjacent pixels.

Claim 6

A method of reducing dark current during the operation of a true two phase, buried channel CCD having a p-type substrate and an n-buried channel, with such CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 , and the second pixel gate to a phase line O 2 , each CCD buried channel gate having transfer and storage regions sequentially formed under each gate, the method comprising the step of: simultaneously applying voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel with the difference in channel potentials of the transfer regions so chosen that a given pixel signal is not mixed with signals contained in adjacent pixels.

Claim 8

A method of reducing dark current during the operation of a true two phase, buried channel CCD having a p-type substrate and an n-buried channel, with such CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 , and the second pixel gate to a phase line O 2 , each CCD buried channel gate having transfer and storage doping regions sequentially formed under each gate, and wherein the transfer regions are more lightly doped (n--) than the storage regions (n-) so that a given pixel signal is not mixed with signals contained in adjacent pixels, comprising simultaneously applying voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel such that the difference in the channel potentials of the two transfer regions is so chosen that a given pixel signal is not mixed with signal contained in adjacent pixels.

Claim 9

A method of reducing dark current during the operation of a true two phase, buried channel CCD having a p-type substrate and an n-buried channel, with such CCD having a repeating series of two gate pixels with the first pixel gate being connected to a phase line O 1 , and the second pixel gate to a phase line O 2 , each CCD buried channel gate having transfer and storage doping regions sequentially formed under each gate, and wherein the transfer regions are more lightly doped (n--) than the storage regions (n-) so that a given pixel signal is not mixed with signals contained in adjacent pixels, comprising simultaneously applying voltages to both phase lines O 1 and O 2 so as to attract holes to the buried channel such that the difference in the channel potentials of the two transfer regions is so chosen that a given pixel signal is not mixed with signal contained in adjacent pixels.