US5113414A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Predistortion arrangement for a digital transmission system
Assignee: US Philips Corp
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Filing: 1990-10-09
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Granted: 1992-05-12
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Expires: 2010-10-09
Abstract
Abstract A predistortion arrangement (9) for a digital transmission system transmits complex input data of a constellation by means of a modulator (14) and a power amplifier (15) which distorts the data. The arrangement comprising a predistortion circuit (11) which predistorts the input data in opposite sense before they pass through the amplifier and a transmit filter (10) which applies oversampled filtered data encoded with 2N bits to the predistortion circuit (11) at the rate k/T. The predistortion circuit (11) is formed from an encoder (20) transforming the filtered 2N-bit encoded data into data encoded with 2M bits (M<N) which address a memory (51) that stores complex predistortion coefficients, and a complex multiplier (52) that multiplies for each data element the 2N bits of the filtered data element by the selected predistortion coefficient for producing predistorted data.
Inventors
- 👤 Georges Karam
- 👤 Said Moridi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:06
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/62; H03; H03F; H03F1/00; H03F1/32; H03F1/3241; H03F1/3247; H04L; H04L27/00; H04L27/32; H04L27/34; H04L27/36; H04L27/366; H04L27/367; H04L27/368; H03F2200/00; H03F2200/438; H03F2200/57
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
184 words
A predistortion arrangement for a digital transmission system which transmits complex input data at a rate defined by a clock having a period T, comprising a power amplifier which introduces nonlinear distortion into data signals being transmitted, a modulator driving the power amplifier, and a predistortion circuit for predistorting input data signals in a sense opposite to distortion introduced in the power amplifier, and providing the predistorted signals to the modulator, characterized in that the predistortion circuit comprises a transmit filter means, responsive to receiving input data, for providing in-phase and quadrature channels of filtered, oversampled data encoded with 2N bits (N bits per channel), at a rate k/T, where k is an integer greater than 1, encoder means for receiving said filtered, oversampled data, and transforming the filtered data encoded with 2N bits into data encoded with 2M bits, where M<N, a memory addressed by the 2M bits, for storing 2 2M complex predistortion coefficients, a complex multiplier, for multiplying the 2N bits of each data element by a selected predistortion coefficient, to produce predistorted input data (F I , F Q ).
Claim 2
Dependent Claim
184 words
A predistortion arrangement for a digital transmission system which transmits complex input data at a rate defined by a clock having a period T, comprising a power amplifier which introduces nonlinear distortion into data signals being transmitted, a modulator driving the power amplifier, and a predistortion circuit for predistorting input data signals in a sense opposite to distortion introduced in the power amplifier, and providing the predistorted signals to the modulator, characterized in that the predistortion circuit comprises a transmit filter means, responsive to receiving input data, for providing in-phase and quadrature channels of filtered, oversampled data encoded with 2N bits (N bits per channel), at a rate k/T, where k is an integer greater than 1, encoder means for receiving said filtered, oversampled data, and transforming the filtered data encoded with 2N bits into data encoded with 2M bits, where M<N, a memory addressed by the 2M bits, for storing 2 2M complex predistortion coefficients, a complex multiplier, for multiplying the 2N bits of each data element by a selected predistortion coefficient, to produce predistorted input data (F I , F Q ).
Claim 3
Dependent Claim
25 words
Arrangement as claimed in claim 1, characterized in that the encoder selects the 2M most significant bits from the 2N bits of the filtered data.
Claim 4
Dependent Claim
38 words
Arrangement as claimed in claim 1, characterized in that for each 2N-bit encoded coordinate (r, q) relating to in-phase and quadrature channels, the encoder determines the modulus (r 2 +q 2 ) and encodes it with 2M bits.
Claim 5
Dependent Claim
33 words
An arrangement as claimed in claim 1, characterized in that the transmit filter is either a digital filter or an analog filter having an output connected to an input of an analog-to-digital converter.
Claim 6
Dependent Claim
49 words
Arrangement as claimed in claim 1, characterized in that the predistortion circuit is adaptive and therefore comprises an adaptation circuit which continuously adapts the predistortion circuit in response to a comparison of the input data and the transmitted data, by means of a demodulation of the transmitted data stream.
Claim 7
Dependent Claim
33 words
An arrangement as claimed in claim 3, characterized in that the transmit filter is either a digital filter or an analog filter having an output connected to an input of an analog-to-digital converter.
Claim 8
Dependent Claim
49 words
Arrangement as claimed in claim 4, characterized in that the predistortion circuit is adaptive and therefore comprises an adaptation circuit which continuously adapts the predistortion circuit in response to a comparison of the input data and the transmitted data, by means of a demodulation of the transmitted data stream.
Claim 9
Dependent Claim
49 words
Arrangement as claimed in claim 2, characterized in that the predistortion circuit is adaptive and therefore comprises an adaptation circuit which continuously adapts the predistortion circuit in response to a comparison of the input data and the transmitted data, by means of a demodulation of the transmitted data stream.
Claim 10
Dependent Claim
49 words
Arrangement as claimed in claim 3, characterized in that the predistortion circuit is adaptive and therefore comprises an adaptation circuit which continuously adapts the predistortion circuit in response to a comparison of the input data and the transmitted data, by means of a demodulation of the transmitted data stream.
Claim 11
Dependent Claim
33 words
An arrangement as claimed in claim 2, characterized in that the transmit filter is either a digital filter or an analog filter having an output connected to an input of an analog-to-digital converter.
Claim 12
Dependent Claim
49 words
Arrangement as claimed in claim 6, characterized in that the predistortion circuit is adaptive and therefore comprises an adaptation circuit which continuously adapts the predistortion circuit in response to a comparison of the input data and the transmitted data, by means of a demodulation of the transmitted data stream.
Claim 13
Dependent Claim
49 words
Arrangement as claimed in claim 10, characterized in that the predistortion circuit is adaptive and therefore comprises an adaptation circuit which continuously adapts the predistortion circuit in response to a comparison of the input data and the transmitted data, by means of a demodulation of the transmitted data stream.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |