US5113374A
Expired / Lapsed
US
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Mos type semiconductor memory device having a word line resetting circuit
Assignee: NEC Corp
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Filing: 1990-08-30
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Granted: 1992-05-12
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Expires: 2010-08-30
Abstract
Abstract A MOS type semiconductor memory device provided with an improved word line reset circuit. The memory device includes word lines and digit lines intersecting with the word lines; a precharge circuit for precharging the digit lines during a precharge period; a row decorder provided for selecting one of the word lines; and the word line reset circuit which includes a word line reset circuit connected between a reference potential and the word lines, respectively, with the word line resetting circuit being adapted to provide a current path between the reference potential and a corresponding one of the word lines during the precharge period and a current path between the reference potential and each of the non-selected word lines during the active period; and a control circuit for setting a resistance of the current path of the word line resetting circuit at a relatively small value during the active period and to a relatively large value during the precharge period.
Inventors
- 👤 Yoshinori Matsui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:01
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
268 words
A MOS type semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; precharge means for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a drive MOS transistor having a source-drain current path coupled between said word line and a first node to which a driving voltage is applied during an active period; first means for supplying a gate of said drive transistor with said first logic signal; a reset MOS transistor having a source-drain current path coupled between said word line and a second node to which said reference voltage is applied; and a control circuit for controlling said reset MOS transistor, said control circuit including a first switch element coupled between a gate of said reset MOS transistor and a third node to which a second voltage is applied, said second voltage having an intermediate voltage between said first voltage and said reference voltage, a second switch element coupled between the gate of said reset MOS transistor and said second output end of said logic decoding circuit, second means for rendering said first switch element conductive during said precharge period and non-conductive during said active period, and third means for rendering said second switch element conductive during said active period and non-conductive during said precharge period.
Claim 2
Dependent Claim
268 words
A MOS type semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; precharge means for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a drive MOS transistor having a source-drain current path coupled between said word line and a first node to which a driving voltage is applied during an active period; first means for supplying a gate of said drive transistor with said first logic signal; a reset MOS transistor having a source-drain current path coupled between said word line and a second node to which said reference voltage is applied; and a control circuit for controlling said reset MOS transistor, said control circuit including a first switch element coupled between a gate of said reset MOS transistor and a third node to which a second voltage is applied, said second voltage having an intermediate voltage between said first voltage and said reference voltage, a second switch element coupled between the gate of said reset MOS transistor and said second output end of said logic decoding circuit, second means for rendering said first switch element conductive during said precharge period and non-conductive during said active period, and third means for rendering said second switch element conductive during said active period and non-conductive during said precharge period.
Claim 3
Dependent Claim
50 words
The semiconductor memory device according to claim 1, in which said first means includes a connection MOS transistor having a source-drain current path coupled between the gate of said drive MOS transistor and said first output end, and said connection MOS transistor having a gate supplied with said first voltage.
Claim 4
Dependent Claim
38 words
The semiconductor memory device according to claim 1, in which said drive MOS transistor and said reset MOS transistor are N-channel MOS transistors, and each of said first and second switch elements is a P-channel type MOS transistor.
Claim 5
Dependent Claim
208 words
A MOS type semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; precharge means for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a first MOS transistor having a source-drain current path coupled between a first end of said word line and a first node to which a driving voltage is applied during an active period; first means for supplying a gate of said first transistor with said first logic signal; a second MOS transistor having a source-drain current path coupled between the first end of said word line and a second node to which said reference voltage is applied; a third MOS transistor having a source-drain current path coupled between a second end of said word line and a third node supplied with said reference voltage; and second means for rendering said third MOS transistor non-conductive during said precharge period and conductive during said active period.
Claim 6
Dependent Claim
208 words
A MOS type semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; precharge means for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a first MOS transistor having a source-drain current path coupled between a first end of said word line and a first node to which a driving voltage is applied during an active period; first means for supplying a gate of said first transistor with said first logic signal; a second MOS transistor having a source-drain current path coupled between the first end of said word line and a second node to which said reference voltage is applied; a third MOS transistor having a source-drain current path coupled between a second end of said word line and a third node supplied with said reference voltage; and second means for rendering said third MOS transistor non-conductive during said precharge period and conductive during said active period.
Claim 7
Dependent Claim
265 words
A semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; a precharge circuit for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a drive transistor having a source-drain current path coupled between said word line and a first node to which a driving voltage is applied during an active period; a first circuit for supplying a gate of said drive transistor with said first logic signal; a reset transistor having a source-drain current path coupled between said word line and a second node to which said reference voltage is applied; and a control circuit for controlling said reset transistor, said control circuit including a first switch element coupled between a gate of said reset transistor and a third node to which a second voltage is applied, said second voltage having an intermediate voltage between said first voltage and said reference voltage, a second switch element coupled between the gate of said reset transistor and said second output end of said logic decoding circuit, a second circuit for rendering said first switch element conductive during said precharge period and non-conductive during said active period, and a third circuit for rendering said second switch element conductive during said active period and non-conductive during said precharge period.
Claim 8
Dependent Claim
265 words
A semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; a precharge circuit for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a drive transistor having a source-drain current path coupled between said word line and a first node to which a driving voltage is applied during an active period; a first circuit for supplying a gate of said drive transistor with said first logic signal; a reset transistor having a source-drain current path coupled between said word line and a second node to which said reference voltage is applied; and a control circuit for controlling said reset transistor, said control circuit including a first switch element coupled between a gate of said reset transistor and a third node to which a second voltage is applied, said second voltage having an intermediate voltage between said first voltage and said reference voltage, a second switch element coupled between the gate of said reset transistor and said second output end of said logic decoding circuit, a second circuit for rendering said first switch element conductive during said precharge period and non-conductive during said active period, and a third circuit for rendering said second switch element conductive during said active period and non-conductive during said precharge period.
Claim 9
Dependent Claim
205 words
A semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; a precharge circuit for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a first transistor having a source-drain current path coupled between a first end of said word line and a first node to which a driving voltage is applied during an active period; a first circuit for supplying a gate of said first transistor with said first logic signal; a second transistor having a source-drain current path coupled between the first end of said word line and a second node to which said reference voltage is applied; a third transistor having a source-drain current path coupled between a second end of said word line and a third node supplied with said reference voltage; and a second circuit for rendering said third transistor non-conductive during said precharge period and conductive during said active period.
Claim 10
Dependent Claim
205 words
A semiconductor memory device comprising a word line; a plurality of digit lines; a plurality of memory cells coupled to said word line and digit lines; a precharge circuit for precharging said digit lines during a precharge period; a logic decoding circuit having a first output end generating a first logic signal and a second output end generating a second logic signal complementary to said first logic signal, said first and second logic signals swinging between a first voltage and a reference voltage; a first transistor having a source-drain current path coupled between a first end of said word line and a first node to which a driving voltage is applied during an active period; a first circuit for supplying a gate of said first transistor with said first logic signal; a second transistor having a source-drain current path coupled between the first end of said word line and a second node to which said reference voltage is applied; a third transistor having a source-drain current path coupled between a second end of said word line and a third node supplied with said reference voltage; and a second circuit for rendering said third transistor non-conductive during said precharge period and conductive during said active period.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |