Circuit arrangement for calculating product sums

Claim 1

Circuit arrangement for forming n products from two multidigit binary numbers Amn, Bkn and for adding said n products, where n is a positive integer greater than one, comprising: an overall array of n parallel multipliers, each comprising a basic array of individual partial product rows formed by respective basic cells; wherein the individual partial product rows of the n basic arrays are interleaved row by row so that the corresponding partial product rows of all n basic arrays are arranged one below the other in respective row groups of n partial product rows each, and wherein the successive partial product rows of all of the successive row groups are interconnected in a pipeline configuration in which each basic cell of a partial product row has an input end connected to adjacent basic cells of the partial product row located thereabove, including a sum input, a carry input, and n A-coefficient inputs, a B-coefficient input connected to a preceeding adjacent basic cell of the same partial product row, an output end connected to adjacent basic cells of the partial product row located therebelow, including a sum output, a carry output, and n A-coefficient outputs, and a B-coefficient output connected to a succeeding adjacent basic cell of the same partial product row, and wherein each basic cell contains: a delay unit for each of n A-coefficients which are applied to the A-coefficient inputs, said delay units being controlled by a half clock signal; an undelayed through connection for a B-coefficient which is applied to the B-coefficient input; an adder fed via respective delay units with the sum signal applied to the sum input, the carry signal applied to the carry input, and a summation input; and a logic gate which combines the B-coefficient with the undelayed A-coefficients to form the partial product thereof and provides said partial product to the summation input of said adder.