Quadratic interpolation for shaded image generation

Claim 2

In a computer graphics system for generating and displaying images of objects on a display device, the images including pixels having pixel values, the images being defined by digital electrical signals representative of the pixel values, the system including elements for processing the digital electrical signals to modify the images displayed on the display device, the improvement comprising A. electrical interpolation circuit means for receiving and processing a first set of digital electrical signals defining first pixel values to generate a second set of digital electrical signals defining second pixel values representative of an interpolated, shaded bitmap image representative of a given object, said second set of digital electrical signals being transmittable to the display device to display said interpolated, shaded bitmap image, said electrical interpolation circuit means including (i) means for executing, on said first set of digital electrical signals, interpolation of order n, where n is an integer greater than one, and (ii) electrical incremental evaluation circuit means, for receiving said first set of digital electrical signals and for executing incremental evaluation of successive ones of said first set of digital electrical signals to generate said second set of digital electrical signals representative of said interpolated, shaded bitmap image, and B. output means, in electrical communication with said electrical interpolation circuit means, and electrically connectable to the display device, for transmitting said second set of digital electrical signals to the display device to display said interpolated, shaded bitmap image representative of an object.

Claim 3

In a system according to claim 1, the further improvement wherein said interpolation circuit means includes forward differencing means for computing forward difference values to incrementally evaluate a given polynomial.

Claim 4

In a system according to claim 2, the further improvement wherein said forward differencing means includes means for computing forward differences in three directions of incremental evaluation.

Claim 5

In a system according to claim 3, the further improvement wherein said forward differencing means includes means for incremental evaluation in two directions associated with a given vector, and in one direction along a predetermined coordinate axis.

Claim 6

In a system according to claim 2, the further improvement wherein said forward differencing means includes means for computing forward differences in two directions of incremental evaluation.

Claim 7

In a system according to claim 5, the further improvement wherein said forward differencing means includes means for computing forward differences in two orthogonal directions of incremental evaluation.

Claim 8

In a system according to claim 5, the further improvement wherein said forward differencing means includes means for computing forward differences in non-orthogonal directions of incremental evaluation.

Claim 9

In a system according to claim 7, the further improvement wherein said forward differencing means includes means for computing forward differences in a first direction of incremental evaluation associated with a given vector, and in a second direction of incremental evaluation along a predetermined coordinate axis.

Claim 10

In a computer graphics system for generating and displaying images of objects on a display device, the images including pixels having pixel values, the images being defined by digital electrical signals representative of the pixel values, the system including elements for processing the digital electrical signals to modify the images displayed on the display device, the improvement comprising A. electrical interpolation circuit means for interpolating a first set of digital electrical signals defining first pixel values to generate a second set of digital electrical signals defining second pixel values representative of an interpolated, shaded bitmap image representative of a given object, said second step of digital electrical signals associated with said bitmap image being storable in a digital electrical storage device and transmittable to the display device to display said interpolated, shaded bitmap image, said electrical interpolation circuit means including (i) means for executing, on said first set of digital electrical signals, interpolation of order n, where n is an integer greater than one, and (ii) electrical non-incremental evaluation circuit means for receiving said first set of digital electrical signals and for executing non-incremental evaluation of successive ones of said first set of digital electrical signals to generate said second set of digital electrical signals representative of said interpolated, shaded bitmap image, and B. output means, in electrical communication with said electrical interpolation means, and electrically connectable to the display device, for transmitting said second set of digital electrical signals to the display device for displaying said interpolated, shaded bitmap image representative of an object.

Claim 11

In a computer graphics system for generating and displaying images of objects on a display device, the images including pixels having pixel values, the images being defined by digital electrical signals representative of the pixel values, the system including elements for processing the digital electrical signals to modify the images displayed on the display device, the improvement comprising A. electrical interpolation circuit means for interpolating a first set of digital electrical signals defining first pixel values to generate a second set of digital electrical signals defining second pixel values representative of an interpolated, shaded bitmap image representative of a given object, said second step of digital electrical signals associated with said bitmap image being storable in a digital electrical storage device and transmittable to the display device to display said interpolated, shaded bitmap image, said electrical interpolation circuit means including (i) means for executing, on said first set of digital electrical signals, interpolation of order n, where n is an integer greater than one, and (ii) electrical non-incremental evaluation circuit means for receiving said first set of digital electrical signals and for executing non-incremental evaluation of successive ones of said first set of digital electrical signals to generate said second set of digital electrical signals representative of said interpolated, shaded bitmap image, and B. output means, in electrical communication with said electrical interpolation means, and electrically connectable to the display device, for transmitting said second set of digital electrical signals to the display device for displaying said interpolated, shaded bitmap image representative of an object.

Claim 12

In a system according to claim 9, the further improvement comprising means for executing spline functions utilizing values of selected control points.

Claim 13

In a system according to claim 9, the further improvement comprising means for executing direct evaluation of a given polynomial.

Claim 14

A digital computer graphics processing system for generating, modifying, and displaying images of objects on a display device, the images including pixels having values, the images being defined by digital electrical signals representative of a stored bitmap image representative of a given object, the bitmap image including interpolated digital electrical signals representative of interpolated pixel values, the digital electrical signals being stored in a memory element having a plurality of memory addresses so that each digital electrical signal is stored in association with a particular memory address, the system comprising: A. electrical address generator circuit means for (i) receiving digital electrical coordinate signals representative of coordinates associated with a first image of the given object, and (ii) generating digital electrical control signals having values representative of successive pixel addresses corresponding to the first image of the object, B. electrical quadratic interpolator circuit means, electrically coupled with said address generator circuit means, for quadratically interpolating, responsive to said control signals, first digital electrical signals representative of first pixel values associated with successive pixel addresses corresponding to the first image of the object, to generate said interpolated digital electrical signals representative of quadratically interpolated pixel values C. electrical storage means, electrically coupled with said address generator circuit means and said quadratic interpolator circuit means, and including a plurality of addressable memory locations, for storing, responsive to said digital electrical control signals, said quadratically interpolated digital electrical signals generated by said quadratic interpolator circuit means, in addressable memory locations corresponding to the addresses represented by said control signal values, so that a quadratically interpolated, shaded bitmap image including quadratically interpolated digital electrical signals is generated, and D. output means, in electrical communication with said electrical interpolation means, and electrically connectable to the display device, for transmitting said quadratically interpolated digital electrical signals stored in said electrical storage means to the display device for displaying said interpolated, shaded bitmap image representative of the object.

Claim 15

A digital computer graphics processing system for generating, modifying, and displaying images of objects on a display device, the images including pixels having values, the images being defined by digital electrical signals representative of a stored bitmap image representative of a given object, the bitmap image including interpolated digital electrical signals representative of interpolated pixel values, the digital electrical signals being stored in a memory element having a plurality of memory addresses so that each digital electrical signal is stored in association with a particular memory address, the system comprising: A. electrical address generator circuit means for (i) receiving digital electrical coordinate signals representative of coordinates associated with a first image of the given object, and (ii) generating digital electrical control signals having values representative of successive pixel addresses corresponding to the first image of the object, B. electrical quadratic interpolator circuit means, electrically coupled with said address generator circuit means, for quadratically interpolating, responsive to said control signals, first digital electrical signals representative of first pixel values associated with successive pixel addresses corresponding to the first image of the object, to generate said interpolated digital electrical signals representative of quadratically interpolated pixel values C. electrical storage means, electrically coupled with said address generator circuit means and said quadratic interpolator circuit means, and including a plurality of addressable memory locations, for storing, responsive to said digital electrical control signals, said quadratically interpolated digital electrical signals generated by said quadratic interpolator circuit means, in addressable memory locations corresponding to the addresses represented by said control signal values, so that a quadratically interpolated, shaded bitmap image including quadratically interpolated digital electrical signals is generated, and D. output means, in electrical communication with said electrical interpolation means, and electrically connectable to the display device, for transmitting said quadratically interpolated digital electrical signals stored in said electrical storage means to the display device for displaying said interpolated, shaded bitmap image representative of the object.

Claim 16

A system according to claim 12, wherein said storage means includes random access memory (RAM) elements including a plurality of addressable memory locations.

Claim 17

A system according to claim 13, wherein said quadratic interpolator means includes a plurality of register means for accumulating resultant data values generated by iterative arithmetic operations.

Claim 18

A system according to claim 14, wherein said quadratic interpolator means includes forward differencing means, electrically coupled with said register means, for calculating forward difference values.