Buffer memory control apparatus using address translation

Claim 2

A buffer memory control apparatus for identifying a row of a buffer memory corresponding to a row of a memory in a digital computer system, said apparatus comprising: a logical to physical address translating means for translating a logical address including a first logical address part to a physical address; a first buffer address array accessed at least with the first logical address part and a second logical address part the second logical address part not being subject to address translation by the translating means; a second buffer address array accessed with said second logical address part for selectively outputting a synonym, which synonym includes common ones of the logical addresses in the buffer memory corresponding to the physical address (10) of the memory in the computer system; a synonym control means for the comparing of the synonym and the physical address and for providing a synonym hit identification to the first buffer address array in response to the synonym and the physical address matching; the buffer memory storing data and being accessed with at least said first logical address part and said second logical address part; a logical hit decoder means for comparing an output of the first buffer address array with the physical address and for enabling a portion of data to be read out of the buffer memory in response to finding a coincidence of the first buffer address array output and the physical address.

Claim 3

The buffer memory control apparatus according to claim 1 further comprising: means connected to the synonym control means for invalidating blocks in said first and second buffer address arrays in which the synonym is included, on the basis of row and group numbers of the blocks, in response to the comparison by said synonym control means.

Claim 4

A buffer memory control apparatus comprising: a first buffer address array arranged to be accessed with a first portion of a logical address and a synonym hit identification, the first buffer address array outputting a first physical address in response thereto, a second buffer address array arranged to be accessed with a TLB physical address translated from a second portion of the logical address, a buffer memory for storing data, a row selecting means for selecting and outputting data from a selected row of the buffer memory, a logical hit decoder means for comparing the first physical address with the TLB physical address and controlling the row selecting means in accordance therewith, and a synonym control means for comparing an output of the second buffer address array with the TLB physical address and selectively indicating a synonym hit in response to the comparison.

Claim 5

A buffer memory control apparatus comprising: a first buffer address array arranged to be accessed with a first portion of a logical address and a synonym hit identification, the first buffer address array outputting a first physical address in response thereto, a second buffer address array arranged to be accessed with a TLB physical address translated from a second portion of the logical address, a buffer memory for storing data, a row selecting means for selecting and outputting data from a selected row of the buffer memory, a logical hit decoder means for comparing the first physical address with the TLB physical address and controlling the row selecting means in accordance therewith, and a synonym control means for comparing an output of the second buffer address array with the TLB physical address and selectively indicating a synonym hit in response to the comparison.

Claim 6

A buffer memory control apparatus comprising: a logical address to physical address translating means for translating a logical address portion to a TLB physical address; a first address array for parallel reading data that are equal in number to a number of rows therein, the first address array being accessed with an address including a first part of the logical address portion which first part is to be subject to the address translation and a second logical address part that is not subject to the translation, the first address array outputting a first physical address row in response to the first and second logical address parts; a second address array for parallel reading data that are equal in number to a multiple of the number of rows, the second address array being accessed with the second logical address part, a hit row number, and a hit synonym number; a comparing means for comparing a row of output data from the second address array with the TLB physical data; a synonym control means for selectively generating the hit row number and the hit synonym number to at least the second address array in response to the comparing of the comparing means.

Claim 7

A buffer memory control apparatus comprising: a logical address to physical address translating means for translating a logical address portion to a TLB physical address; a first address array for parallel reading data that are equal in number to a number of rows therein, the first address array being accessed with an address including a first part of the logical address portion which first part is to be subject to the address translation and a second logical address part that is not subject to the translation, the first address array outputting a first physical address row in response to the first and second logical address parts; a second address array for parallel reading data that are equal in number to a multiple of the number of rows, the second address array being accessed with the second logical address part, a hit row number, and a hit synonym number; a comparing means for comparing a row of output data from the second address array with the TLB physical data; a synonym control means for selectively generating the hit row number and the hit synonym number to at least the second address array in response to the comparing of the comparing means.

Claim 8

A buffer memory control apparatus for identifying a buffer corresponding to a memory in a digital computer system, said apparatus comprising: a logical address to physical address translating means for translating a received portion of a logical address to a physical address; a first address array accessed with a first part of the logical address portion, and a second part of the logical address which is not subject to the address translation; a second address array accessed with at least a part of physical address and with said second part of the logical address; a buffer for storing data, the buffer being accessed with at least said first part and said second part of the logical address; a logical hit decoder means for comparing the physical address with an output of the first address array; a selecting means controlled by the logical hit decoder means for selecting data from the buffer in response to the logical hit decoder means comparison; and, means for comparing an output of said second address array with the physical address to detect a hit of a synonym.

Claim 9

A buffer memory control apparatus for identifying a buffer corresponding to a memory in a digital computer system, said apparatus comprising: a logical address to physical address translating means for translating a received portion of a logical address to a physical address; a first address array accessed with a first part of the logical address portion, and a second part of the logical address which is not subject to the address translation; a second address array accessed with at least a part of physical address and with said second part of the logical address; a buffer for storing data, the buffer being accessed with at least said first part and said second part of the logical address; a logical hit decoder means for comparing the physical address with an output of the first address array; a selecting means controlled by the logical hit decoder means for selecting data from the buffer in response to the logical hit decoder means comparison; and, means for comparing an output of said second address array with the physical address to detect a hit of a synonym.

Claim 10

A buffer memory control apparatus for identifying a synonym hit in a set associative cache, the buffer memory control apparatus comprising: a logical address to physical address translating means for reading a logical address portion and outputting a TLB physical address; a first address array accessed with a first part of the logical address portion and with a second part of the logical address that is not subject to address translation for selectively outputting a first physical address in response to said first and second parts; a logical hit decoder means for comparing the TLB and first physical addresses and for selectively outputting a confirmation signal indicating a coincidence between said TLB physical address and said first physical address; a second address array accessed with said logical address second part for selectively outputting a synonym; a comparing means for comparing the synonym with the TLB physical address; a synonym control means for outputting a hit row number and a hit synonym in response to the comparison between said TLB physical address and said synonym; a buffer selectively accessed by said the logical address first and second parts; a selecting means for selecting a corresponding portion of data stored in the buffer, the selecting means being operatively connected with the logical hit decoder means to be enabled to output the selected corresponding data portion in response to the confirmation signal.

Claim 11

A buffer memory control apparatus for identifying a synonym hit in a set associative cache, the buffer memory control apparatus comprising: a logical address to physical address translating means for reading a logical address portion and outputting a TLB physical address; a first address array accessed with a first part of the logical address portion and with a second part of the logical address that is not subject to address translation for selectively outputting a first physical address in response to said first and second parts; a logical hit decoder means for comparing the TLB and first physical addresses and for selectively outputting a confirmation signal indicating a coincidence between said TLB physical address and said first physical address; a second address array accessed with said logical address second part for selectively outputting a synonym; a comparing means for comparing the synonym with the TLB physical address; a synonym control means for outputting a hit row number and a hit synonym in response to the comparison between said TLB physical address and said synonym; a buffer selectively accessed by said the logical address first and second parts; a selecting means for selecting a corresponding portion of data stored in the buffer, the selecting means being operatively connected with the logical hit decoder means to be enabled to output the selected corresponding data portion in response to the confirmation signal.