US5107249A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Intrusion detection system having improved immunity to false alarm
Assignee: C&K Systems Inc
•
Filing: 1990-10-16
•
Granted: 1992-04-21
•
Expires: 2010-10-16
Abstract
Abstract A multi-sensor intrusion detection system having improved immunity to false alarm is disclosed. The sensor being less susceptible to the generation of false alarm has its output signal processed and held. The held signal is supplied to a logic gate which receives directly the signal from the other sensor. The output of the logic gate generates an alarm signal.
Inventors
- 👤 Richard A. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:42
CPC Classifications
G; G08; G08B; G08B13/00; G08B13/16; G08B13/1654; G08B13/1681; G08B13/1672
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
212 words
An intrusion detection system comprising: a first detecting means for detecting an intrusion in a volume of space by a first physical phenomenon and for generating a first signal in response to the detection of said intrusion, said first signal being in one of two possible states, a first state representative of detection of presence of said intrusion and a second state representative of detection of absence of said intrusion; a second detecting means for detecting an intrusion in said volume of space by a second physical phenomenon, different from the first phenomenon for generating a second signal in response to the detection of said intrusion, said second signal being in one of two possible states, a first state representative of detection of presence of said intrusion and a second state representative of detection of absence of said intrusion; said second detecting means being less susceptible to false alarm than said first detecting means; first signal holding means for holding said second signal and for producing a held second signal; and logic means for receiving directly said first signal and directly said held second signal and for generating an alarm signal in response to said first signal being in said first state and said held second signal being in said first state.
Claim 2
Dependent Claim
212 words
An intrusion detection system comprising: a first detecting means for detecting an intrusion in a volume of space by a first physical phenomenon and for generating a first signal in response to the detection of said intrusion, said first signal being in one of two possible states, a first state representative of detection of presence of said intrusion and a second state representative of detection of absence of said intrusion; a second detecting means for detecting an intrusion in said volume of space by a second physical phenomenon, different from the first phenomenon for generating a second signal in response to the detection of said intrusion, said second signal being in one of two possible states, a first state representative of detection of presence of said intrusion and a second state representative of detection of absence of said intrusion; said second detecting means being less susceptible to false alarm than said first detecting means; first signal holding means for holding said second signal and for producing a held second signal; and logic means for receiving directly said first signal and directly said held second signal and for generating an alarm signal in response to said first signal being in said first state and said held second signal being in said first state.
Claim 3
Dependent Claim
14 words
The system of claim 1 wherein said first signal holding means is a register.
Claim 4
Dependent Claim
22 words
The system of claim 1 further comprising: second signal holding means for receiving said alarm signal and for holding said alarm signal.
Claim 5
Dependent Claim
18 words
The system of claim 1 wherein said logic means further comprising: means for delaying said held second signal.
Claim 6
Dependent Claim
13 words
The system of claim 4 wherein said delaying means comprises a resistor-capacitor circuit.
Claim 7
Dependent Claim
57 words
The system of claim 1 wherein said logic means comprises: a comparator means having two inputs, a first input for receiving said first signal; and means for receiving said held second signal and for processing said held second signal to produce a processed second signal and for providing same to said second input of said comparator means.
Claim 8
Dependent Claim
18 words
The system of claim 6 wherein said processing means further comprising: means for delaying said held second signal.
Claim 9
Dependent Claim
13 words
The system of claim 7 wherein said delaying means comprises a resistor-capacitor circuit.
Claim 10
Dependent Claim
86 words
The system of claim 1 wherein said logic means comprises: a comparator means having two inputs, a first input for receiving said first signal and a second input for receiving a reference signal and for producing a compared first signal; gate means having two inputs, a first input for receiving said compared signal; and means for receiving said held second signal and for processing said held second signal to produce a processed second signal and for providing same to said second input of said gate means.
Claim 11
Dependent Claim
17 words
The system of claim 9 wherein said processing further comprising: means for delaying said held second signal.
Claim 12
Dependent Claim
13 words
The system of claim 10 wherein said delaying means comprises a resistor-capacitor circuit.
Claim 13
Dependent Claim
56 words
The system of claim 1 wherein said logic means comprises: gate means having two inputs, a first input for receiving said first signal; and means for receiving said held second signal and for processing said held second signal to produce a processed second signal and for providing same to said second input of said gate means.
Claim 14
Dependent Claim
17 words
The system of claim 12 wherein said processing further comprising: means for delaying said held second signal.
Claim 15
Dependent Claim
13 words
The system of claim 13 wherein said delaying means comprises a resistor-capacitor circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |