US5107138A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with battery serving as power source having CMOS analog and digital circuits and regulated stepped up voltage source
Assignee: Seiko Precision Inc
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Filing: 1989-04-07
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Granted: 1992-04-21
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Expires: 2009-04-07
Abstract
Abstract An integrated circuit comprises a logic circuit connectable to a battery power supply to energize the logic circuit. A converter generates a stepped up voltage supply from the battery power supply and an analog circuit is receptive of the stepped up voltage supply for controlling the operation of other circuitry. The analog circuit and the logic circuit comprise CMOS transistors integrated on the same chip.
Inventors
- 👤 Yoichi Seki
- 👤 Hiroyuki Saito
- 👤 Michio Taniwaki
- 👤 Teruyo Hayakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:22
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156; G; G04; G04G; G04G19/00; G04G19/02
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
75 words
An integrated circuit with a battery source serving as a power source, comprising: a logic circuit operable by a battery source; a converter for generating a regulated stepped up voltage source stepped up from said battery source; and a comparator used to regulate the stepped up voltage source and operable by said stepped up voltage source, wherein said logic circuit and said comparator are composed of C-MOS transistors and are integrated on the same chip.
Claim 2
Dependent Claim
75 words
An integrated circuit with a battery source serving as a power source, comprising: a logic circuit operable by a battery source; a converter for generating a regulated stepped up voltage source stepped up from said battery source; and a comparator used to regulate the stepped up voltage source and operable by said stepped up voltage source, wherein said logic circuit and said comparator are composed of C-MOS transistors and are integrated on the same chip.
References Cited (Backward Citations)
US3818484A
Cited
US3955353A
Cited
US4279010A
Cited
US4053821A
Cited
US4268763A
Cited
US4683382A
Cited
US4730122A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |