Matrix circuit of fm stereo multiplex demodulation circuit

Claim 2

A matrix circuit comprising: a first output node; a second output node; a first resistor having a first terminal connected to receive a current signal and a second terminal coupled to said first output node; a second resistor having a first terminal connected to said first terminal of said first resistor; a first bipolar transistor having a first collector coupled to a second terminal of said second resistor, a first emitter connected to a circuit ground and a first base connected to said first collector; and a second bipolar transistor having a second collector connected to said second output node, a second emitter connected to said circuit ground and a second base connected to said first base.

Claim 3

A matrix circuit according to claim 1, wherein said first collector is coupled to said second terminal of said second resistor through a third bipolar transistor having a third emitter connected to said second terminal of said second resistor, a third base connected to a first preset potential and a third collector connected to said first collector of said first bipolar transistor.

Claim 4

A matrix circuit according to claim 2, wherein said second terminal of said first resistor is coupled to said first output node through a fourth bipolar transistor having a fourth collector coupled to said first output node, a fourth base connected to a second preset potential and a fourth emitter connected to said second terminal of said first resistor.

Claim 5

A matrix circuit comprising: a first output node; a second output node; a first resistor having a first terminal connected to receive a current signal and a second terminal coupled to said first output node; a second resistor having a first terminal connected to said first terminal of said first resistor and a second terminal connected to ground; a third resistor having a first terminal coupled to said second output node and a second terminal connected to ground; a first current source connected at a first terminal to a first predetermined potential; a second current source connected at a first terminal to said first predetermined potential; a first bipolar transistor having a first collector connected to a second terminal of said first current source, a first base connected to said collector and a first emitter coupled to said first terminal of said third resistor; a second bipolar transistor having a second collector connected to a second terminal of said second current source, a second base connected to said first base of said first bipolar transistor and a second emitter connected to said first terminal of said first resistor; wherein said third resistor is coupled to said second output node by a third bipolar transistor having a third collector connected to a second output node, a third base connected to said second collector of said second bipolar transistor and a third emitter connected to said first terminal of said third resistor; wherein said second terminal of said first resistor is coupled to said first output node through a fourth bipolar transistor having a fourth collector coupled to said first output node, a fourth base connected to a first preset potential and a fourth emitter connected to said second terminal of said first resistor; wherein said fourth collector of said fourth bipolar transistor is coupled to said first output node by a fifth bipolar transistor having a fifth emitter connected to said first output node, a base connected to said fourth collector of said fourth bipolar transistor and a fifth collector connected to said fourth emitter of said fourth bipolar transistor and a fourth resistor is connected between said fifth base and said fifth emitter of said fifth bipolar transistor.

Claim 6

A matrix circuit comprising: a first output node; a second output node; a first resistor having a first terminal connected to receive a current signal and a second terminal coupled to said first output node; a second resistor having a first terminal connected to said first terminal of said first resistor and a second terminal connected to ground; a third resistor having a first terminal coupled to said second output node and a second terminal connected to ground; a first current source connected at a first terminal to a first predetermined potential; a second current source connected at a first terminal to said first predetermined potential; a first bipolar transistor having a first collector connected to a second terminal of said first current source, a first base connected to said collector and a first emitter coupled to said first terminal of said third resistor; a second bipolar transistor having a second collector connected to a second terminal of said second current source, a second base connected to said first base of said first bipolar transistor and a second emitter connected to said first terminal of said first resistor; wherein said third resistor is coupled to said second output node by a third bipolar transistor having a third collector connected to a second output node, a third base connected to said second collector of said second bipolar transistor and a third emitter connected to said first terminal of said third resistor; wherein said second terminal of said first resistor is coupled to said first output node through a fourth bipolar transistor having a fourth collector coupled to said first output node, a fourth base connected to a first preset potential and a fourth emitter connected to said second terminal of said first resistor; wherein said fourth collector of said fourth bipolar transistor is coupled to said first output node by a fifth bipolar transistor having a fifth emitter connected to said first output node, a base connected to said fourth collector of said fourth bipolar transistor and a fifth collector connected to said fourth emitter of said fourth bipolar transistor and a fourth resistor is connected between said fifth base and said fifth emitter of said fifth bipolar transistor.

Claim 7

A matrix circuit according to claim 4, further comprising: switching decoder means, connected between said first output node and said second output node, for decoding a signal from said first and second output nodes.

Claim 8

A matrix circuit according to claim 5, wherein said switching decoder means comprises: a sixth bipolar transistor having a sixth collector connected to a left signal output, a sixth base connected to a first signal input and a sixth emitter connected to said first output node; a seventh bipolar transistor having a seventh collector connected to a right signal output, a seventh base connected to a second signal input and a seventh emitter connected to said sixth emitter of said sixth bipolar transistor; an eighth bipolar transistor having an eighth collector connected to said left signal output, an eighth base connected to said seventh base of said seventh bipolar transistor and an eighth emitter connected to said second output node; and a ninth bipolar transistor having a ninth collector connected to said seventh collector of said seventh bipolar transistor, a ninth base connected to said first signal input and a ninth emitter connected to said eighth emitter of said eighth bipolar transistor.

Claim 9

A matrix circuit comprising: a first output node; a second output node; a first resistor having a first terminal connected to receive a current signal and a second terminal coupled to said first output node; a first bipolar transistor having a first collector connected to said first terminal of said first resistor, a first emitter coupled to a circuit ground and a first base connected to said first collector; a second bipolar transistor having a second collector connected to said second output node, a second emitter coupled to said circuit ground and a second base connected to said first base; a second resistor connected between said first emitter of said first bipolar transistor and said circuit ground; and a third resistor connected between said second emitter of said second transistor and said circuit ground, said third resistor having the same resistance value as said second resistor.

Claim 10

A matrix circuit comprising: a first output node; a second output node; a first resistor having a first terminal connected to receive a current signal and a second terminal coupled to said first output node; a first bipolar transistor having a first collector connected to said first terminal of said first resistor, a first emitter coupled to a circuit ground and a first base connected to said first collector; a second bipolar transistor having a second collector connected to said second output node, a second emitter coupled to said circuit ground and a second base connected to said first base; a second resistor connected between said first emitter of said first bipolar transistor and said circuit ground; and a third resistor connected between said second emitter of said second transistor and said circuit ground, said third resistor having the same resistance value as said second resistor.

Claim 11

A matrix circuit according to claim 7, wherein said second terminal of said first resistor is coupled to said first output node through a third bipolar transistor having a third collector connected to said first output node, a third base connected to a first preset potential and a third emitter connected to said second terminal of said first resistor.

Claim 12

A matrix circuit comprising: a first resistor having a first terminal connected to receive a current signal and a second terminal coupled to a first output node; a first current source connected at a first terminal to a first predetermined potential; a second current source connected at a first terminal to said first predetermined potential; a first bipolar transistor having a first collector connected to a second terminal of said first current source, a first base connected to said collector and a first emitter coupled to a circuit ground; a second bipolar transistor having a second collector connected to a second terminal of said second current source, a second base connected to said first base of said first bipolar transistor and a second emitter connected to said first terminal of said first resistor; a third bipolar transistor having a third collector connected to a second output node, a third base connected to said second collector of said second bipolar transistor and a third emitter connected to said first emitter; a second resistor having a first terminal connected to said second emitter of said second bipolar transistor and a second terminal connected to said circuit ground; and a third resistor having a first terminal connected to said first emitter of said first bipolar transistor and a second terminal connected to said circuit ground, said third resistor having the same resistance value as said second resistor.

Claim 13

A matrix circuit comprising: a first resistor having a first terminal connected to receive a current signal and a second terminal coupled to a first output node; a first current source connected at a first terminal to a first predetermined potential; a second current source connected at a first terminal to said first predetermined potential; a first bipolar transistor having a first collector connected to a second terminal of said first current source, a first base connected to said collector and a first emitter coupled to a circuit ground; a second bipolar transistor having a second collector connected to a second terminal of said second current source, a second base connected to said first base of said first bipolar transistor and a second emitter connected to said first terminal of said first resistor; a third bipolar transistor having a third collector connected to a second output node, a third base connected to said second collector of said second bipolar transistor and a third emitter connected to said first emitter; a second resistor having a first terminal connected to said second emitter of said second bipolar transistor and a second terminal connected to said circuit ground; and a third resistor having a first terminal connected to said first emitter of said first bipolar transistor and a second terminal connected to said circuit ground, said third resistor having the same resistance value as said second resistor.

Claim 14

A matrix circuit according to claim 9, wherein said second terminal of said first resistor is coupled to said first output node through a fourth bipolar transistor having a fourth collector coupled to said first output node, a fourth base connected a second predetermined potential and a fourth emitter connected to said second terminal of said first resistor; wherein said fourth collector of said fourth bipolar transistor is coupled to said first output node through a fifth bipolar transistor having a fifth bipolar emitter connected to said first output node, a fifth base connected to said fourth collector of said fourth bipolar transistor and a fifth collector connected to said fourth emitter of said fourth bipolar transistor and a fourth resistor is connected between said fifth base and fifth emitter of said fifth bipolar transistor.

Claim 15

A matrix circuit according to claim 10, further comprising: switching decoder means, connected between said first and second output nodes, for decoding a signal from said first and second output nodes.

Claim 16

A matrix circuit according to claim 11, wherein said switching decoder means comprises: a sixth bipolar transistor having a sixth collector connected to a left signal output, a sixth base connected to a first signal input and a sixth emitter connected to said first output node; a seventh bipolar transistor having a seventh collector connected to a right signal output, a seventh base connected to a second signal input and a seventh emitter connected to said sixth emitter of said sixth bipolar transistor; an eighth bipolar transistor having an eighth collector connected to said left signal output, an eighth base connected to said seventh base of said seventh bipolar transistor and an eighth emitter connected to said second output node; and a ninth bipolar transistor having a ninth collector connected to said seventh collector of said seventh bipolar transistor, a ninth base connected to said first signal input and a ninth emitter connected to said eighth emitter of said eighth bipolar transistor.